Method of obtaining planar semipolar gallium nitride surfaces

US9978845B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9978845-B2
Application numberUS-201515304189-A
CountryUS
Kind codeB2
Filing dateApr 15, 2015
Priority dateApr 16, 2014
Publication dateMay 22, 2018
Grant dateMay 22, 2018

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Abstract

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Methods and structures for forming flat, continuous, planar, epitaxial layers of semipolar III-nitride materials on patterned sapphire substrates are described. Semipolar GaN may be grown from inclined c-plane facets on a patterned sapphire substrate, and coalesced to form a continuous layer of semipolar III-nitride semiconductor over the sapphire substrate. Planarization of the layer is followed by crystal regrowth using a nitrogen carrier gas to produce a flat, microfabrication-grade, process surface of semipolar III-nitride semiconductor across the substrate. Quality multiple quantum wells can be fabricated in the regrown semipolar material.

First claim

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What is claimed is: 1. A method for forming an epitaxial layer of semipolar gallium-nitride on a substrate, the method comprising growing semipolar gallium-nitride adjacent to crystal-growth surfaces of a patterned sapphire substrate, wherein the crystal-growth surfaces comprise a first portion of a plurality of surfaces of different orientations formed on the patterned sapphire substrate that are not masked by a masking material that masks a remaining second portion of the plurality of surfaces and wherein the crystal-growth surfaces have one select orientation of the different orientations. 2. The method of claim 1 , further comprising forming a low-temperature aluminum-nitride or a low-temperature gallium-nitride buffer layer at the crystal-growth surfaces. 3. The method of claim 2 , wherein either of the low-temperature buffer layers are formed below a temperature of approximately 600° C. 4. The method of claim 1 , further comprising: planarizing the grown semipolar gallium-nitride; and regrowing the semipolar gallium-nitride using a nitrogen carrier gas. 5. The method of claim 4 , wherein regrowing the semipolar gallium-nitride comprises regrowth conditions that do not include a hydrogen carrier gas. 6. The method of claim 4 , wherein the nitrogen carrier gas is N 2 . 7. The method of claim 4 , wherein regrowing the semipolar gallium-nitride comprises growing the semipolar gallium-nitride using metal-organic chemical vapor deposition. 8. The method of claim 7 , wherein a temperature during regrowth is between approximately 980° C. and approximately 1070° C. 9. The method of claim 7 , wherein a pressure during regrowth is between approximately 100 mbar and approximately 300 mbar. 10. The method of claim 7 , wherein a flow rate of NH 3 gas during regrowth is between approximately 0.5 slm and approximately 4 slm. 11. The method of claim 7 , wherein a flow rate of trimethylgallium or triethylgallium during regrowth is between approximately 30 sccm and approximately 50 sccm. 12. The method of claim 7 , wherein a growth rate during regrowth is between 1 μm/hr and approximately 2 μm/hr. 13. The method of claim 4 , wherein growing semipolar gallium-nitride and regrowing semipolar gallium-nitride comprise growing the gallium-nitride with a (20 2 1) facet approximately parallel to a process surface of the substrate. 14. The method of claim 4 , wherein planarizing the grown semipolar gallium-nitride comprises planarization by chemical-mechanical polishing. 15. The method of claim 4 , further comprising, prior to growing semipolar gallium-nitride, forming the masking layer to cover the plurality of surfaces of the patterned sapphire substrate. 16. The method of claim 15 , wherein forming the masking layer comprises depositing a material conformally by a vapor deposition process. 17. The method of claim 16 , further comprising removing the conformally deposited material from the crystal-growth surfaces. 18. A substrate comprising: a patterned sapphire substrate having a plurality of surfaces at different orientations and a masking layer formed over all of the plurality of surfaces except crystal-growth surfaces that are a portion of the plurality of surfaces having one select orientation of the different orientations; and a semipolar gallium-nitride epitaxial layer formed over the patterned sapphire substrate. 19. The substrate of claim 18 , wherein the patterned sapphire substrate has a (22 4 3) facet approximately parallel to a process surface of the substrate and a c-plane facet approximately parallel to the crystal-growth surfaces. 20. The substrate of claim 18 , wherein the patterned sapphire substrate comprises an array of trenches with the crystal-growth surfaces forming inclined walls of the trenches. 21. The substrate of claim 20 , wherein a spacing of the trenches is between approximately 0.25 microns and approximately 10 microns, and a depth of the trenches is between approximately 50 nanometers and approximately 2 microns. 22. The substrate of claim 20 , wherein the epitaxial gallium-nitride layer coalesces above the trenches to form a continuous and planar semiconductor layer across the substrate. 23. The substrate of claim 22 , wherein a roughness of a surface of the planer semiconductor layer measured over a 15 μm×15 μm area is less than 5 nm root-mean-square. 24. The substrate of claim 18 , further comprising a buffer layer between the crystal-growth surfaces and the epitaxial gallium-nitride. 25. The substrate of claim 24 , wherein the buffer layer comprises aluminum-nitride. 26. The substrate of claim 22 , wherein the planar semipolar gallium-nitride epitaxial layer has a single and continuous planar surface across the substrate that is approximately parallel to a (20 2 1) facet of the semipolar gallium-nitride.

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What does patent US9978845B2 cover?
Methods and structures for forming flat, continuous, planar, epitaxial layers of semipolar III-nitride materials on patterned sapphire substrates are described. Semipolar GaN may be grown from inclined c-plane facets on a patterned sapphire substrate, and coalesced to form a continuous layer of semipolar III-nitride semiconductor over the sapphire substrate. Planarization of the layer is follow…
Who is the assignee on this patent?
Univ Yale
What technology area does this patent fall under?
Primary CPC classification H10P14/24. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 22 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).