Integrated circuit and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9978764-B2
Application number	US-201615133394-A
Country	US
Kind code	B2
Filing date	Apr 20, 2016
Priority date	Dec 29, 2015
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.

First claim

The invention claimed is:

1. An integrated circuit comprising at least one high-voltage MOS (HV) transistor, and at least one capacitor, wherein:
a gate stack of the HV transistor comprises a first insulating layer over a semiconductor layer and a gate electrode made of a first polysilicon layer;
the capacitor comprises a first electrode made of the first polysilicon layer over the semiconductor layer, a second electrode made of a second polysilicon layer extending at least partly over the first electrode, and a stack comprising a first silicon oxide layer coated with a silicon nitride layer that is coated with a second silicon oxide layer, said stack extending between the second electrode and the semiconductor layer and further extending between the second electrode and the first electrode;
first spacers made of silicon oxide laterally bordering the second electrode and the gate stack of the HV transistor; and
second spacers made of silicon nitride laterally bordering the first spacers,
wherein the first silicon oxide layer and the silicon nitride layer extend beyond sides of the second electrode and underneath the first and second spacers laterally bordering the second electrode; and
wherein the first silicon oxide layer and the silicon nitride layer also extend between the first spacers and sides of the gate stack of the HV transistor, and further extend underneath the first and second spacers laterally bordering the gate stack of the HV transistor.

2. The integrated circuit of claim 1 , further comprising at least one floating-gate MOS (NVM) transistor, wherein:
a gate stack of the NVM transistor comprises a second insulating layer over the semiconductor layer and a first gate electrode made of the first polysilicon layer, and a second gate electrode made of the second polysilicon layer, with the second oxide layer, the nitride layer, and the first oxide layer positioned between the first and second gate electrodes; and
third spacers laterally bordering the gate stack of the NVM transistor, said third spacers further laterally bordering the second spacers at the HV transistor and the second electrode of the capacitor.

3. The integrated circuit of claim 2 , further comprising at least one low-voltage MOS (LV) transistor, wherein:
a gate stack of the LV transistor comprises a third insulating layer over the semiconductor layer and a gate electrode made of the second polysilicon layer; and
fourth spacers laterally bordering sides of the gate stack of the LV transistor and the third spacers at the HV transistor and the second electrode of the capacitor.

4. An integrated circuit, comprising:
a semiconductor substrate including a first semiconducting region and an insulating region;
a high voltage transistor including a gate stack formed over the first semiconducting region, the gate stack of the high voltage transistor including a gate electrode formed of a first polysilicon material; and
a capacitor formed over the insulating region, the capacitor including a first plate formed of the first polysilicon material and a second plate formed of a second polysilicon material and an insulating material layer positioned between the first and second plates, wherein the insulating material layer extends beyond sidewalls of the second plate and is further positioned on sidewalls of the gate stack of the high voltage transistor;
wherein the first polysilicon material of the gate stack of the high voltage transistor and first plate of the capacitor are patterned from a first polysilicon layer over said semiconductor substrate and the second polysilicon material of the second plate is formed from a second polysilicon layer over the first polysilicon layer; and
sidewall spacer structures laterally bordering the insulating material layer on sidewalls of the gate stack of the high voltage transistor and on sidewalls of the first and second plates of the capacitor, said sidewall spacer structures positioned over the insulating material layer that extends beyond sidewalls of the second plate.

5. The integrated circuit of claim 4 , wherein the semiconductor substrate further includes a second semiconducting region and further comprising:
a non-volatile memory transistor including a gate stack formed over the second semiconducting region, the gate stack of the non-volatile memory transistor including a floating gate electrode formed of the first polysilicon material and a control gate electrode formed of the second polysilicon material,
wherein the first polysilicon material of the gate stack of the high voltage transistor, the floating gate electrode of the non-volatile memory transistor and the first plate of the capacitor are patterned from the first polysilicon layer; and
wherein the second polysilicon material of the control gate electrode of the non-volatile memory transistor and the second plate of the capacitor are patterned from the second polysilicon layer.

6. The integrated circuit of claim 5 , wherein the insulating material layer between the first and second plates of the capacitor is further present between the floating gate electrode and control gate electrode of the non-volatile memory transistor.

7. The integrated circuit of claim 5 :
wherein the sidewall spacer structures are not present laterally bordering the gate stack of the non-volatile memory transistor; and further comprising:
additional sidewall spacer structures laterally bordering the sidewall spacer structures at the first and second plates of the capacitor and the high voltage transistor, said additional sidewall spacer structures further positioned on sidewalls of the gate stack of the non-volatile memory transistor.

8. The integrated circuit of claim 7 , wherein the additional sidewall spacer structures laterally bordering the sidewall spacer structures at the second plate are positioned over the insulating material layer that extends beyond sidewalls of the second plate.

9. The integrated circuit of claim 4 , wherein the semiconductor substrate further includes a second semiconducting region and further comprising:
a low voltage transistor including a gate stack formed over the second semiconducting region, the gate stack of the low voltage transistor including a gate electrode formed of the second polysilicon material,
wherein the second polysilicon material of the gate electrode of the low voltage transistor and second plate of the capacitor are patterned from the second polysilicon layer.

10. The integrated circuit of claim 9 , further comprising:
additional sidewall spacer structures positioned adjacent sidewalls of the gate stack of the low voltage transistor.

11. An integrated circuit, comprising:
a semiconductor substrate including a first semiconducting region and an insulating region;
a high voltage transistor including a gate stack formed over the first semiconducting region, the gate stack of the high voltage transistor including a gate electrode formed of a first polysilicon material;
a capacitor formed over the insulating region, the capacitor including a first plate formed of the first polysilicon material and a second plate formed of a second polysilicon material and an insulating material layer positioned between the first and second plates, wherein the insulating material layer extends beyond sidewalls of the second plate and is further positioned on sidewalls of the gate stack of the high voltage transistor;
wherein the first polysilicon material of the gate stack of the high voltage transistor and first plate of the capacitor are patterned from a first polysilicon layer over said semiconductor substrate and the second polysilicon material of the second plate is formed from a second polysili

Assignees

• St Microelectronics Crolles 2 Sas

Inventors

• Piazza Fausto
• Lagrasta Sebastien
• Bianchi Raul Andres
• Jeannot Simon

Classifications

• H10P50/264

  by chemical means · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/416

  of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10D64/01306 Primary

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon · CPC title