Three-dimensional (3D) semiconductor memory devices

Patent metadata

Field	Value
Publication number	US-9978752-B2
Application number	US-201615373922-A
Country	US
Kind code	B2
Filing date	Dec 9, 2016
Priority date	Jan 15, 2016
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

A three-dimensional (3D) semiconductor memory device may include a substrate including a cell array region and a connection region, an electrode structure including pluralities of first and second electrodes that are vertically and alternately stacked on a surface of the substrate, extending in a first direction that is parallel to the surface of the substrate, and may include a stair step structure on the connection region, first and second string selection electrodes that extend in the first direction on the electrode structure and spaced apart from each other in a second direction that is parallel to the surface of the substrate and perpendicular to the first direction. The first and second string selection electrodes may each include an electrode portion on the cell array region and a pad portion that extends from the electrode portion in the first direction and on the connection region. Widths in the second direction of the pad portions may be different from widths in the second direction of the respective electrode portions.

First claim

What is claimed is:

1. A three-dimensional (3D) semiconductor memory device comprising:
a substrate comprising a cell array region and a connection region;
an electrode structure comprising pluralities of first and second electrodes that are vertically and alternately stacked on a surface of the substrate, the electrode structure extending in a first direction that is parallel to the surface of the substrate and the electrode structure comprising a stair step structure on the connection region; and
first and second string selection electrodes that extend in the first direction on the electrode structure, the first and second string selection electrodes being spaced apart from each other in a second direction that is parallel to the surface of the substrate and perpendicular to the first direction,
wherein the first and second string selection electrodes each comprise an electrode portion on the cell array region and a pad portion extending from the electrode portion in the first direction on the connection region, and
wherein widths in the second direction of the pad portions are different from widths in the second direction of the respective electrode portions.

2. The 3D semiconductor memory device of claim 1 ,
wherein the widths of the electrode portions of the first and second string selection electrodes are substantially equal to each other, and
wherein the width of the pad portion of the first string selection electrode is different from the width of the pad portion of the second string selection electrode.

3. The 3D semiconductor memory device of claim 1 ,
wherein the width of the pad portion of the first string selection electrode decreases as a distance from the electrode portion of the first string selection electrode increases, and
wherein the width of the pad portion of the second string selection electrode increases as a distance from the electrode portion of the second string selection electrode increases.

4. The 3D semiconductor memory device of claim 1 , wherein a distance between the electrode portions of the first and second string selection electrodes is substantially equal to a distance between the pad portions of the first and second string selection electrodes.

5. The 3D semiconductor memory device of claim 1 ,
wherein the electrode structure has first and second sidewalls opposite to each other that extend in the first direction,
wherein the first string selection electrode has a sidewall that is aligned with the first sidewall of the electrode structure, and
wherein the second string selection electrode has a sidewall that is aligned with the second sidewall of the electrode structure.

6. The 3D semiconductor memory device of claim 1 ,
wherein ones of the first electrodes comprise a first pad region on the connection region, the first pad region being exposed by an adjacent second electrode,
wherein ones of the second electrodes comprise a second pad region on the connection region, the second pad region being exposed by an adjacent first electrode, and
wherein the second pad regions of the ones of the second electrodes are adjacent in the second direction to the first pad regions of respective ones of the first electrodes.

7. The 3D semiconductor memory device of claim 6 ,
wherein an uppermost layer of the electrode structure comprises an uppermost second electrode, and
wherein the first and second string selection electrodes expose the second pad region of the uppermost second electrode.

8. The 3D semiconductor memory device of claim 7 , wherein a width of the second pad region of the uppermost second electrode is greater than widths of the second pad regions of others of the second electrodes.

9. The 3D semiconductor memory device of claim 1 , wherein an uppermost layer of the electrode structure comprises an uppermost second electrode, the uppermost second electrode comprising:
first and second electrode portions that extend in the first direction on the cell array region, the first and second electrode portions spaced apart from each other in the second direction; and
a protrusion on the connection region to horizontally connect the first and second electrode portions,
wherein the uppermost second electrode exposes a portion of an adjacent first electrode.

10. The 3D semiconductor memory device of claim 9 ,
wherein the first electrode portion of the uppermost second electrode comprises a first width in the second direction that is the same as a first width in the second direction of the second electrode portion of the uppermost second electrode,
wherein the protrusion of the uppermost second electrode has a second width in the second direction, and
wherein the second width is greater than the first width.

11. The 3D semiconductor memory device of claim 9 ,
wherein the first electrode portion of the uppermost second electrode overlaps the first string selection electrode as viewed from a plan view, and
wherein the second electrode portion of the uppermost second electrode overlaps the second string selection electrode as viewed from a plan view.

12. The 3D semiconductor memory device of claim 9 ,
wherein the uppermost second electrode comprises an isolation region horizontally separating the first and second electrode portions from each other, and
wherein a length of the isolation region of the uppermost second electrode in the first direction is greater than lengths of the first and second string selection electrodes in the first direction.

13. The 3D semiconductor memory device of claim 1 ,
wherein an uppermost layer of the electrode structure comprises an uppermost second electrode,
wherein the 3D semiconductor memory device further comprises an isolation insulating pattern between the first and second string selection electrodes, the isolation insulating pattern penetrating the uppermost second electrode,
wherein the isolation insulating pattern comprises a linear portion that extends in the first direction on the cell array region and a bending portion that extends from the linear portion on the connection region, the bending portion being bent with respect to the linear portion.

14. The 3D semiconductor memory device of claim 1 , further comprising:
first vertical channels on the cell array region that penetrate the first string selection electrode and the electrode structure;
second vertical channels on the cell array region that penetrate the second string selection electrode and the electrode structure; and
dummy vertical channels between the first and second string selection electrodes on the cell array region, the dummy vertical channels penetrating the electrode structure.

15. A three-dimensional (3D) semiconductor memory device comprising:
a substrate comprising a cell array region and a connection region; and
an electrode structure comprising pluralities of first and second electrodes that are vertically and alternately stacked on a surface of the substrate, the electrode structure extending in a first direction that is parallel to the surface of the substrate and the electrode structure comprising a stair step structure on the connection region,
wherein ones of the first electrodes comprise a first pad region on the connection region, the first pad region being exposed by an adjacent second electrode,
wherein ones of the second electrodes comprise a second pad region on the connection region, the second pad region being exposed by an adjacent first electrode,
wherein the second pad regions of the ones of the second electrodes are adjacent, in a second direction that is parallel to the surface of the substrate and perpend

Assignees

• Kim Kyoung Hoon
• Jo Sangyoun
• Samsung Electronics Co Ltd

Inventors

• Kim Kyoung-Hoon
• Jo Sangyoun

Classifications

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H01L23/5283

  Electricity · mapped topic

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• H01L27/1052 Primary

  Electricity · mapped topic

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title