Fan-out semiconductor package module

Patent metadata

Field	Value
Publication number	US-9978731-B1
Application number	US-201715800951-A
Country	US
Kind code	B1
Filing date	Nov 1, 2017
Priority date	Dec 28, 2016
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip with connection pads on its active surface disposed in the through-hole and a first encapsulant encapsulating at least portions of the first connection member and the semiconductor chip. A second connection member is disposed below the first connection member and the semiconductor chip. A first heat dissipation member is formed in the first connection member. A component package is disposed on the fan-out semiconductor package and includes a wiring substrate connected to the first connection member through connection terminals, electronic components disposed on the wiring substrate, a second encapsulant encapsulating at least portions of the electronic components, and a second heat dissipation member formed in the wiring substrate. At least one of the electronic components is connected to the first heat dissipation member through the second heat dissipation member.

First claim

What is claimed is:

1. A fan-out semiconductor package module comprising:
a fan-out semiconductor package comprising
a first connection member having a through-hole,
a semiconductor chip disposed in the through-hole of the first connection member, the semiconductor chip having an active surface and an inactive surface opposing the active surface, the active surface having connection pads disposed on the active surface,
a first encapsulant encapsulating at least portions of the first connection member and the semiconductor chip,
a second connection member disposed below the first connection member and the semiconductor chip, and
a first heat dissipation member formed in the first connection member or the through-hole, the first connection member and the second connection member each comprising redistribution layers electrically connected to the connection pads of the semiconductor chip; and

a component package disposed on the fan-out semiconductor package, the component package comprising:
a wiring substrate connected to the first connection member through connection terminals,
a plurality of electronic components disposed on the wiring substrate,
a second encapsulant encapsulating at least portions of the plurality of electronic components, and
a second heat dissipation member formed in the wiring substrate,

wherein at least one of the plurality of electronic components of the component package is connected to the first heat dissipation member through the second heat dissipation member.

2. The fan-out semiconductor package module of claim 1 , wherein the first and second heat dissipation members overlap the at least one electronic component connected to the first and second heat dissipation members when viewed in plan.

3. The fan-out semiconductor package module of claim 1 , wherein the first connection member comprises a plurality of first vias electrically connecting a redistribution layer of the first connection member disposed on one layer to a redistribution layer of the first connection member of a different layer,
the first heat dissipation member comprises a plurality of second vias formed in a region different from a region in which the plurality of first vias are formed in the first connection member and connected to the second heat dissipation member, and
the first plurality of vias and the second plurality of vias are disposed to satisfy the condition: P1>P2, where P1 is a pitch between the plurality of first vias and P2 is a pitch between the plurality of second vias.

4. The fan-out semiconductor package module of claim 3 , wherein the first plurality of vias and the second plurality of vias are disposed to satisfy the condition: S1>S2 where S1 is an area of the region in which the plurality of first vias of the first connection member are formed and S2 is an area of the region in which the plurality of second vias are formed.

5. The fan-out semiconductor package module of claim 1 , wherein the first heat dissipation member comprises at least one bar-shaped via formed in the first connection member and connected to the second heat dissipation member.

6. The fan-out semiconductor package module of claim 1 , wherein the semiconductor chip and the first heat dissipation member are disposed side by side with each other in the through-hole, and
the first heat dissipation member comprises a metal block disposed in the through-hole and connected to the second heat dissipation member.

7. The fan-out semiconductor package module of claim 1 , wherein the through-hole comprises a first through-hole in which the semiconductor chip is disposed and a second through-hole in which the first heat dissipation member is disposed, and
the first heat dissipation member comprises a metal block disposed in the second through-hole and connected to the second heat dissipation member.

8. The fan-out semiconductor package module of claim 1 , wherein the second heat dissipation member comprises a plurality of stacked vias.

9. The fan-out semiconductor package module of claim 1 , wherein the fan-out semiconductor package further comprises a third heat dissipation member formed in the second connection member, and
the third heat dissipation member is connected to the first and second heat dissipation members.

10. The fan-out semiconductor package module of claim 9 , wherein the third heat dissipation member comprises a plurality of stacked vias or at least one bar-shaped via.

11. The fan-out semiconductor package module of claim 1 , wherein the semiconductor chip comprises a transceiver integrated circuit (IC).

12. The fan-out semiconductor package module of claim 11 , wherein the plurality of electronic components comprise a power amplifier (PA) comprising a body having circuits formed therein, connection pads disposed on the body, and vias penetrating through the body,
wherein the connection pads of the power amplifier are electrically connected to the wiring substrate through wire bonding, and
a lower surface of the power amplifier is connected to the second heat dissipation member.

13. The fan-out semiconductor package module of claim 12 , wherein a ground layer is disposed on the lower surface of the power amplifier, the ground layer being connected to the second heat dissipation member through a conductive adhesive.

14. The fan-out semiconductor package module of claim 12 , wherein the plurality of electronic components further comprise an antenna, a controller, a bulk acoustic wave filter, and
the second heat dissipation member is connected to the power amplifier among the plurality of electronic components.

15. The fan-out semiconductor package module of claim 1 , wherein the first connection member comprises
a first insulating layer,
a first redistribution layer in contact with the second connection member and embedded in a first surface of the first insulating layer,
a second redistribution layer disposed on a second surface of the first insulating layer opposing the first surface of the first insulating layer,
a second insulating layer disposed on the first insulating layer and covering the second redistribution layer, and
a third redistribution layer disposed on the second insulating layer,
wherein the first to third redistribution layers are electrically connected to the connection pads.

16. The fan-out semiconductor package module of claim 1 , wherein the first connection member comprises
a first insulating layer,
a first redistribution layer disposed on a lower surface of the first insulating layer,
a second redistribution layer disposed on an upper surface of the first insulating layer,
a second insulating layer disposed on the lower surface of the first insulating layer and covering the first redistribution layer,
a third insulating layer disposed on the upper surface of the first insulating layer and covering the second redistribution layer,
a third redistribution layer disposed on a lower surface of the second insulating layer, and
a fourth redistribution layer disposed on an upper surface of the third insulating layer,
wherein the first to fourth redistribution layers are electrically connected to the connection pads.

Assignees

• Samsung Electro Mech

Inventors

• Kim Won Gi

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title