Wafer backside interconnect structure connected to TSVs

Patent metadata

Field	Value
Publication number	US-9978708-B2
Application number	US-201615269613-A
Country	US
Kind code	B2
Filing date	Sep 19, 2016
Priority date	Sep 22, 2009
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.

First claim

What is claimed is:

1. A method for forming an integrated circuit structure, the method comprising:
forming a conductive via in a semiconductor substrate having an active device at a front surface, the semiconductor substrate further having a back surface opposite the front surface;
exposing the conductive via at the back surface of the semiconductor substrate by reducing a thickness of the semiconductor substrate;
after exposing the conductive via at the back surface of the semiconductor substrate, patterning an opening extending from the back surface of the semiconductor substrate into the semiconductor substrate;
forming a first metal feature in the opening and contacting the conductive via; and
forming a bump overlying and electrically connected to the first metal feature relative the back surface of the semiconductor substrate.

2. The method of claim 1 , wherein patterning the opening comprises exposing the conductive via, wherein the opening has a greater horizontal dimension than the conductive via, and wherein forming the first metal feature comprises:
forming a dielectric isolation layer on sidewalls and a lateral surface of the opening;
forming a conductive barrier layer on the dielectric isolation layer; and
filling remaining portions of the opening with a metal.

3. The method of claim 2 , further comprising, prior to forming the conductive barrier layer, removing a portion of the dielectric isolation layer contacting the conductive via.

4. The method of claim 1 , wherein patterning the opening comprises recessing the conductive via so that the back surface of the semiconductor substrate is higher than a surface of the conductive via, and wherein the opening exposes the surface of the conductive via.

5. The method of claim 1 further comprising forming a second metal feature between the first metal feature and the bump.

6. The method of claim 5 , wherein the second metal feature comprises a dual damascene structure.

7. The method of claim 5 further comprising forming a dielectric layer on the back surface of the semiconductor substrate, wherein the second metal feature is formed in the dielectric layer.

8. The method of claim 1 , wherein horizontal dimensions of the first metal feature are greater than respective horizontal dimensions of the conductive via in a top-down view of the integrated circuit structure.

9. A method comprising:
planarizing a semiconductor substrate to expose a conductive via extending from a front surface of the semiconductor substrate to a back surface of the semiconductor substrate, wherein an active device is disposed at the front surface of the semiconductor substrate;
after exposing the conductive via, etching a trench opening in a semiconductor substrate, wherein the conductive via extends from the trench opening to the front surface of the semiconductor substrate;
depositing a first dielectric liner along sidewalls and a bottom surface of the trench opening;
depositing a conductive barrier layer over the first dielectric liner in the trench opening; and
forming a conductive line in the trench opening over the conductive barrier layer and electrically connected to the conductive via.

10. The method of claim 9 further comprising before etching the trench opening and after exposing the conductive via, recessing the conductive via from a back surface of the semiconductor substrate opposite the front surface.

11. The method of claim 9 , wherein at least a portion of the bottom surface of the trench opening is disposed at a different level than a surface of the conductive via exposed by the trench opening.

12. The method of claim 9 further comprising while patterning the trench opening, patterning an additional trench opening in the semiconductor substrate, wherein a portion of the semiconductor substrate is disposed between the trench opening and the additional trench opening.

13. The method of claim 12 further comprising forming an additional conductive line in the additional trench opening.

14. The method of claim 9 further comprising forming an external connector on a surface of the conductive line opposite the conductive via.

15. The method of claim 9 further comprising:
forming a dual-damascene interconnect structure on a surface of the conductive line opposite the conductive via; and
forming an external connector over the dual-damascene interconnect structure.

16. A method comprising:
exposing a conductive via at a back side of a semiconductor substrate, the conductive via extending from the back side of the semiconductor substrate to a front side of the semiconductor substrate, an active device is disposed at the front side of the semiconductor substrate;
after exposing the conductive via, etching a trench opening in the semiconductor substrate, etching the trench opening comprises:
etching the conductive via to define a first opening extending form the back side of the semiconductor substrate into the semiconductor substrate; and
etching the semiconductor substrate to widen the first opening and define the trench opening;

forming a conductive line in the trench opening and electrically connected to the conductive via; and
forming a solder region electrically connected to the conductive line.

17. The method of claim 16 , wherein an isolation layer is disposed between a sidewall of the conductive via and the semiconductor substrate, and wherein etching the trench opening comprises removing a portion of the isolation layer exposed by the first opening.

18. The method of claim 16 further comprising:
depositing dielectric isolation layer along sidewalls and a bottom surface of the first opening; and
depositing a conductive barrier layer over the dielectric isolation layer, wherein the conductive barrier layer extends though the dielectric isolation layer, and wherein forming the conductive line comprises forming the conductive line over the conductive barrier layer.

19. The method of claim 18 further comprising removing a portion of the dielectric isolation layer directly over the conductive via using a patterned mask, wherein at least a portion of the patterned mask is disposed in the trench opening.

20. The method of claim 18 further comprising forming a dual-damascene interconnect between the conductive line and the solder region.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Ming-Fa
• Chiou Wen-Chih
• Shue Shau-Lin

Classifications

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0249

  wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture · CPC title