Self-aligned multiple spacer patterning schemes for advanced nanometer technology

Patent metadata

Field	Value
Publication number	US-9978596-B2
Application number	US-201615377629-A
Country	US
Kind code	B2
Filing date	Dec 13, 2016
Priority date	Jun 20, 2014
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

The present disclosure provides forming nanostructures with precision dimension control and minimum lithographic related errors for features with dimension under 14 nanometers and beyond. A self-aligned multiple spacer patterning (SAMSP) process is provided herein and the process utilizes minimum lithographic exposure process, but rather multiple deposition/etching process to incrementally reduce feature sizes formed in the mask along the manufacturing process, until a desired extreme small dimension nanostructures are formed in a mask layer.

First claim

What is claimed is:

1. A method for forming nanometer features in a material layer disposed on a substrate comprising:
performing multiple deposition processes on a substrate to form multiple mask layers on a material layer disposed on the substrate, where the multiple mask layer includes N mask layers, wherein N is a positive integer greater than or equal to 2, wherein each mask layer has substantially the same width; and
selectively etching a portion of the mask layers of the multiple mask layers from the substrate to form a first group of openings in between each of the mask layers, wherein the mask layers being removed from the substrate are a (N−1) layer and a (N−(1+2X)) layer, wherein X is an integer less than N, wherein the first group of openings has a dimension less than 14 nm.

2. The method of claim 1 , wherein the multiple mask layers are fabricated from dielectric materials.

3. The method of claim 1 , wherein at least two mask layers of the multiple mask layers are fabricated from different materials.

4. The method of claim 1 , further comprising:
performing an etching process to etching the material layer through the first group of openings defined in the multiple mask layers to form a second group of openings in the material layer.

5. The method of claim 1 , wherein selectively etching a portion of the mask layers further comprises:
performing more than one etching process to remove different mask layers of the multiple mask layers.

6. The method of claim 1 , wherein a first patterned mask layer of the multiple mask layers is a polysilicon or amorphous silicon layer.

7. The method of claim 6 , wherein a second patterned mask layer of the multiple mask layers is silicon nitride and a third patterned mask layer is amorphous carbon.

Assignees

• Applied Materials Inc

Inventors

• Zhang Ying
• Mitra Uday
• Gopalraja Praburam
• Nemani Srinivas D
• Chung Hua

Classifications

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10P76/405 Primary

  characterised by their composition, e.g. multilayer masks · CPC title