Memory devices providing a refresh request and memory controllers responsive to a refresh request

Patent metadata

Field	Value
Publication number	US-9978430-B2
Application number	US-201313733884-A
Country	US
Kind code	B2
Filing date	Jan 3, 2013
Priority date	Apr 24, 2012
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

A memory system includes at least one memory device and a memory controller. The at least one memory device includes a refresh request circuit that generates refresh request signals at timings based on data retention times of memory cells, such as based on individual data retention times of a memory cell row. The memory controller schedules operation commands for the at least one memory device in response to the received refresh request signals.

First claim

What is claimed is:

1. A memory device, comprising:
a memory cell array including a plurality of rows of memory cells;
a refresh request circuit configured to issue requests for refresh operations to an external device; and
control logic configured to receive commands from the external device and control the memory device in accordance with the received commands,
wherein the refresh request circuit is configured to issue a request for a refresh operation for a first row of memory cells of the plurality of rows of memory cells to the external device, the request for the refresh operation issued to the external device in conjunction with an address of the first row of memory cells, and the control logic is configured to receive a first refresh command to refresh the first row from the external device and cause a refresh operation of the first row of memory cells in response to the first refresh command, and
wherein the refresh request circuit is configured to issue each request for a refresh operation as a refresh request signal via a first terminal of the memory device.

2. The memory device of claim 1 , wherein the refresh request circuit is configured to issue requests for refresh operations for a plurality of first rows of memory cells of the memory device at a first refresh rate and issue requests for refresh operations for a plurality of second rows of memory cells of the memory device at one or more second refresh rates, each of the one or more second refresh rates being higher than the first refresh rate.

3. The memory device of claim 2 ,
wherein the refresh request circuit comprises a lookup table configured to store addresses of the plurality of second rows of memory cells at table entries of the lookup table, and
wherein a sequential access of the entries of the lookup table determines a timing of issuance of requests for refresh operations for the second rows of memory cells.

4. The memory device of claim 3 ,
wherein the lookup table is configured to store addresses of the plurality of first rows of memory cells at table entries of the lookup table, and
wherein sequential access of the entries of the lookup table determine a timing of issuance of requests for refresh operations for the first rows of memory cells.

5. The memory device of claim 3 ,
wherein the refresh request circuit comprises an address counter configured to generate sequential addresses of the memory cells of the memory cell array, including addresses of the first and second rows of memory cells, the refresh request circuit configured to issue requests for refresh operations for rows of memory cells identified by the sequential addresses generated by the address counter.

6. The memory device of claim 5 , further comprising a multiplexer, the multiplexer configured to select sequential addresses generated by the address counter and addresses of the plurality of second rows of memory cells output by the lookup table and provide the selected address for output to the external device.

7. The memory device of claim 3 , further comprising a lookup table pointer generator configured to output and regularly change a table pointing signal used to access a table entry of the lookup table corresponding to the table pointing signal.

8. The memory device of claim 7 ,
wherein the lookup table includes empty table entries between table entries containing addresses of second rows of memory cells acting to regulate a timing between a sequential output of the addresses of the second rows of memory cells.

9. The memory device of claim 7 ,
wherein entries of the lookup table include wait information, and
wherein a timing of a change of the table pointing signal is responsive to the wait information.

10. The memory device of claim 7 ,
wherein entries of the lookup table include wait information, and
wherein a timing of a change of the table pointing signal from identifying a first entry of the lookup table to identifying a second entry of the lookup table is responsive to wait information stored with the first entry of the lookup table.

11. A memory controller comprising:
a command generator configured to generate memory commands in response to externally received command requests from a host;
a scheduler configured to generate a command queue providing a sequential list of memory commands to be issued to a memory device external to the memory controller, the sequential list of memory commands comprising the memory commands generated by the command generator in response to the command requests from the host;
at least one terminal to receive a refresh request from the memory device; and
a storage unit configured to store one or more addresses of the memory device received with the refresh request from the memory device,
wherein the scheduler is configured to alter the sequential list of memory commands in the command queue to insert refresh commands into the command queue, the refresh commands including the one or more addresses of the memory device stored in the storage unit to identify locations of the memory device to be refreshed.

12. The memory controller of claim 11 , wherein the storage unit is configured to store non-sequential addresses of the memory device to provide different refresh rates for different memory locations of the memory device.

13. The memory controller of claim 11 , wherein the scheduler is configured to provide refresh commands for first rows of memory cells at a first rate and provide refresh commands for second rows of memory cells at one or more second rates, the second rates being higher than the first rate.

14. The memory controller of claim 11 , further comprising a buffer configured to receive the one or more addresses of the memory device from the memory device.

15. The memory controller of claim 14 , wherein the at least one terminal comprises a data mask pin configured to receive the refresh request from the memory controller.

16. A memory system comprising the memory device of claim 1 and an external device, wherein the external device is a memory controller connected to the memory device to provide commands to the memory device.

17. The memory controller of claim 11 , wherein the scheduler is configured to generate the sequential list of memory commands in the command queue prior to receipt of the refresh request from the memory device and to alter the sequential list of memory commands in the command queue after receipt of the refresh request from the memory device.

18. The memory controller of claim 17 , wherein the memory controller is implemented in a single semiconductor chip.

19. The memory device of claim 1 , wherein the memory device is implemented in a single semiconductor chip.

20. The memory device of claim 1 , wherein the first terminal is separate from all data terminals and all address terminals of the memory device.

21. The memory device of claim 1 , wherein the refresh request circuit is configured to transmit the address of the first row of memory cells to the external device via terminals of the memory device used for transmitting data of the memory device.

22. The memory device of claim 1 , wherein the refresh request circuit is configured to transmit the address of the first row of memory cells to the external device at the same time as transmitting the request for the refresh operation.

23. The memory device of claim 1 , wherein the refresh request signal is a first logic level transmitted to the external device via the f

Assignees

• Seo Eun Sung
• Park Chul Woo
• Hwang Hong Sun
• Samsung Electronics Co Ltd

Inventors

• Seo Eun-Sung
• Park Chul-Woo
• Hwang Hong-Sun

Classifications

• G11C11/40611 Primary

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title

• G11C7/00 Primary

  Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413) · CPC title

• G11C11/408

  Address circuits · CPC title

• G11C11/406 Primary

  Management or control of the refreshing or charge-regeneration cycles · CPC title