Display controller and semiconductor integrated circuit devices including the same

Patent metadata

Field	Value
Publication number	US-9978336-B2
Application number	US-201514984365-A
Country	US
Kind code	B2
Filing date	Dec 30, 2015
Priority date	Dec 31, 2014
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

A display controller includes a first register set by an open operating system, a second register set by a secure operating system, a first data input circuit configured to read normal data according to set information in the first register, a second data input circuit configured to read secure data according to set information in the second register, and a data processor configured to blend and output the normal data with the secure data to display the secure data over the normal data.

First claim

What is claimed is:

1. A display controller for controlling a display device, the display controller comprising:
a first register set by an open operating system;
a second register set by a secure operating system;
a first data input circuit configured to read normal data according to set information in the first register;
a second data input circuit configured to read secure data according to set information in the second register; and
a data processor configured to blend the normal data with the secure data to generate blended data for display, the blended data including the secure data superimposed over the normal data,
wherein the set information in the first register comprises first set information identifying the first data input circuit and second set information identifying the second data input circuit and the set information in the second register comprises the second set information identifying the second data input circuit.

2. The display controller of claim 1 , wherein the set information in the second register further comprises a secure flag.

3. The display controller of claim 2 , wherein the second data input circuit reads the normal data when the secure flag is set to a first value and reads the secure data when the secure flag is set to a second value.

4. The display controller of claim 1 , further comprising a secure controller configured to control the second data input circuit according to the set information in the second register.

5. The display controller of claim 4 , wherein the second register comprises secure screen attribute information and the display controller controls the data processor to blend the normal data with the secure data according to the secure screen attribute information.

6. The display controller of claim 1 , wherein the first register is set by either of the open operating system and the secure operating system according to a value of a first control port corresponding to the first register and the second register is set by the secure operating system according to a value of a second control port corresponding to the second register.

7. The display controller of claim 1 , further comprising a third data input circuit configured to read normal data according to the set information in the first register,
wherein the second data input circuit is set to read data corresponding to a topmost layer and the first and third data input circuits are set to read data corresponding to at least one lower layer.

8. The display controller of claim 7 , wherein the set information in the first register is maintained after conversion from a normal mode into a secure mode.

9. A semiconductor integrated circuit comprising:
a processor configured to drive an open operating system and a secure operating system;
a display controller configured to control a display device according to control of the processor; and
a bus configured to transfer a control signal and data between the processor and the display controller,
wherein the display controller blends normal data with secure data to generate blended data in a secure mode, the blended data comprising secure image data of the secure data superimposed over the normal data,
wherein the secure image data graphically provides information indicating that an unauthorized user is currently accessing or attempting to access the secure data,
wherein the display controller comprises first and second registers and a plurality of data input circuits,
wherein at least one of the data input circuits identified by the first register is configured to read the normal data, and
wherein at least one of the data input circuits identified by the second register is configured to read the secure data.

10. The semiconductor integrated circuit of claim 9 , wherein the first register is set by the open operating system and the second register is set by the secure operating system.

11. The semiconductor integrated circuit device of claim 10 , wherein when a secure flag bit is set in the second register, the display controller assigns at least one of the data input circuits to read the secure data.

12. The semiconductor integrated circuit device of claim 11 , wherein the second register comprises set information corresponding to at least one of the data input circuits and the display controller further comprises a secure controller configured to control the at least one of the data input circuits according to the set information in the second register.

13. The semiconductor integrated circuit of claim 12 , wherein the display controller further comprises a data processor configured to blend the normal data with the secure data according to control of the secure controller and the secure controller controls the data processor to blend the normal data with the secure data according to attribute information of a secure screen on which the secure data is displayed.

14. The semiconductor integrated circuit of claim 10 , wherein when a secure flag bit is not set in the second register, the display controller assigns the data input circuits to read the normal data according to set information in the first register.

15. A semiconductor integrated circuit comprising:
a central processing unit (CPU) configured to run an open operating system (OS) during a non-secure mode and a secure OS during a secure mode;
a plurality of control circuits;
a first register configured to store information indicating a first set of the control circuits allocated for retrieving normal image data of the non-secure mode;
a second register configured to store information indicating a second set of the control circuits allocated for retrieving secure image data of the secure mode generated by the secure operating system; and
a data processor configured to blend the normal image data with the secure image data for output to a display device during the secure mode,
wherein the first set of the control circuits identified by the first register is configured to read the normal image data, and
wherein the second set of the control circuits identified by the second register is configured to read the secure image data.

16. The semiconductor integrated circuit of claim 15 , wherein the semiconductor integrated circuit is a system-on chip.

17. The semiconductor integrated circuit of claim 15 , wherein the second register includes a flag indicating whether a mode of the circuit is set to the non-secure mode or the secure mode.

18. The semiconductor integrated circuit of claim 15 , wherein the open OS is prevented from updating the second register.

19. The semiconductor integrated circuit of claim 15 , wherein the blending places the normal image data into a first layer of a screen of the display device, the secure image data into second layer of the screen, where the second layer is above the first layer.

20. The semiconductor integrated circuit of claim 19 , wherein the secure image data graphically provides information indicating that a security violation has occurred.

Assignees

• Samsung Electonics Co Ltd
• Samsung Electronics Co Ltd

Inventors

• Kim Kyoung Man
• Yoon Sung Chul
• Meng Xiangyu

Classifications

• G09G2340/125

  wherein one of the images is motion video · CPC title

• G09G5/003 Primary

  Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto (specific for a CRT G09G1/165; for a flat panel G09G3/2092) · CPC title

• G09G5/377

  for mixing or overlaying two or more graphic patterns (G09G5/02, G09G5/397 take precedence) · CPC title

• G09G2340/12

  Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels · CPC title

• G09G2358/00

  Arrangements for display data security · CPC title