Capacitance to code converter with sigma-delta modulator

Patent metadata

Field	Value
Publication number	US-9977551-B2
Application number	US-201514832529-A
Country	US
Kind code	B2
Filing date	Aug 21, 2015
Priority date	Nov 14, 2006
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

Apparatuses and methods of converting a capacitance measured on a sense element to a digital value are described. One apparatus includes a modulator having a modulator capacitor, a sense element selectively coupled in a feedback loop of the modulator to operate as a switching capacitor. The apparatus also includes a first switch coupled between a voltage source and a first node of the switching capacitor and a second switch coupled between the first node of the switching capacitor and a first node of the modulator capacitor. The switching capacitor provides a charge current to the modulator capacitor via the second switch. The modulator measures a capacitance of the sense element and converts the measured capacitance to a digital code representing the capacitance.

First claim

What is claimed is:

1. An apparatus comprising:
a modulator comprising a modulator capacitor;
a capacitor comprising a first plate and a second plate;
a switching circuit comprising:
a first switch coupled between a voltage source and the first plate of the capacitor;
a second switch coupled between the second plate of the capacitor and the voltage source; and
a third switch coupled between the first plate of the capacitor and a ground node,

wherein the capacitor is to provide a charge current to the modulator capacitor, and wherein the modulator is to measure a capacitance of the capacitor and convert the capacitance to a digital code representing the capacitance, wherein:
in a first configuration, the first switch is closed to connect the voltage source to the first plate of the capacitor and the second switch is open to disconnect the voltage source from the second plate of the capacitor, and
in a second configuration, the first switch is open to disconnect the voltage source from the first plate of the capacitor and the second switch is closed to connect the voltage source to the second plate of the capacitor.

2. The apparatus of claim 1 , wherein, in the second configuration, an output of the modulator is to switch the capacitor as a switching capacitor in a feedback loop of the modulator.

3. The apparatus of claim 1 , further comprising a digital filter coupled to receive an output of the modulator, wherein the output of the modulator is a digital output bitstream, wherein the digital output bitstream is a continuous, single-bit stream and the digital code is a multi-bit value.

4. The apparatus of claim 1 , further comprising, in the first configuration:
a plurality of drive lines; and
a plurality of sense lines, wherein one of the plurality of drive lines is coupled to the first plate of the capacitor and one of the plurality of sense lines is coupled to the second plate of the capacitor, and wherein the capacitance is a mutual capacitance.

5. The apparatus of claim 1 , wherein, in the second configuration, the second plate of the capacitor is a single electrode and the first plate is coupled to the ground node, and wherein the capacitance is a self capacitance.

6. The apparatus of claim 1 , further comprising a spread-spectrum clock to control the first switch and the third switch.

7. The apparatus of claim 1 , further comprising:
an oscillator to provide an oscillator signal; and
a pseudo-random signal (PRS) circuit to receive the oscillator signal and to generate a PRS to control the first switch and the third switch.

8. The apparatus of claim 1 , further comprising a voltage-controlled oscillator (VCO) to control the first switch and the third switch.

9. The apparatus of claim 1 , wherein the modulator is a sigma-delta modulator.

10. The apparatus of claim 9 , wherein the sigma-delta modulator comprises a comparator, wherein the comparator is to toggle an output signal when a voltage on the modulator capacitor crosses a reference voltage.

11. The apparatus of claim 10 , wherein the output signal of the is to activate charging of the modulator capacitor when the voltage on the modulator capacitor is below the reference voltage and to activate discharging of the modulator capacitor when the voltage on the modulator capacitor is above the reference voltage.

12. The apparatus of claim 11 , further comprising a discharge resistor to discharge the modulator capacitor, wherein the comparator is to activate the discharging of the modulator capacitor using the discharge resistor.

13. A method comprising:
operating a switching circuit in a first configuration, the switching circuit comprising a first switch, a second switch, and a third switch;
measuring, by a modulator, a first capacitance of a capacitor comprising a first plate and a second plate, wherein, in the first configuration, the first switch is closed to connect a voltage source to the first plate of the capacitor and the second switch is open to disconnect the voltage source from the second plate of the capacitor,
operating the switching circuit in a second configuration;
measuring, by the modulator, a second capacitance of the capacitor, wherein, in the second configuration, the first switch is open to disconnect the voltage source from the first plate of the capacitor and the second switch is closed to connect the voltage source to the second plate of the capacitor; and
converting the first capacitance to a first digital value and converting the second capacitance to a second digital value.

14. The method of claim 13 , wherein the measuring the first capacitance comprises:
applying a drive signal to a drive line using an excitation signal source, the drive line being coupled to the first plate of the capacitor; and
sensing, by the modulator, the drive signal on a sense line, the sense line being coupled to the second plate of the capacitor, wherein the first capacitance is a mutual capacitance.

15. The method of claim 13 , wherein, in the second configuration, switching the capacitor as a switching capacitor in a feedback loop of the modulator.

16. The method of claim 13 , wherein, in the second configuration, the measuring the second capacitance comprises:
applying a charge to the second plate of the capacitor; and
sensing, by the modulator, the charge on the second plate of the capacitor, wherein the second capacitance is a self capacitance.

17. An apparatus comprising:
a capacitor comprising a first plate and a second plate;
a switching circuit coupled to a voltage source, the switching circuit comprising:
a first switch coupled between the voltage source and the first plate of the capacitor;
a second switch coupled between the second plate of the capacitor and the voltage source; and
a third switch coupled between the first plate of the capacitor and a ground node, wherein, in a first configuration, the first switch is closed to connect the voltage source to the first plate of the capacitor and the second switch is open to disconnect the voltage source from the second plate of the capacitor, and wherein, in a second configuration, the first switch is open to disconnect the voltage source from the first plate of the capacitor and the second switch is closed to connect the voltage source to the second plate of the capacitor; and

a measurement circuit coupled to the switching circuit to measure a first capacitance of the capacitor while the switching circuit is in the first configuration and to measure a second capacitance of the capacitor while the switching circuit is in the second configuration, and to convert the first capacitance to a first digital code and the second capacitance to a second digital code.

18. The apparatus of claim 17 , wherein the measurement circuit comprises a modulator, wherein a control circuit is to control the first switch, second switch, and third switch based at least in part by an output of the modulator.

19. The apparatus of claim 17 , wherein the measurement circuit comprises:
a modulator capacitor;
a comparator to receive a reference voltage and a voltage on the modulator capacitor;
a latch coupled to an output of the comparator, the latch to latch the output of the comparator based on a clock signal; and
a control circuit to receive an output of the latch and the clock signal to control the first switch and the second switch.

Assignees

• Cypress Semiconductor Corp

Inventors

• Kremin Viktor

Classifications

• H03M11/02

  Details · CPC title

• G06F3/044 Primary

  by capacitive means · CPC title

• G06F3/0416

  Control or interface arrangements specially adapted for digitisers · CPC title

• G06F3/0446

  using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes · CPC title

• G06F3/04166 Primary

  Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving (Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184) · CPC title