Integrated circuit reliability assessment apparatus and method

Patent metadata

Field	Value
Publication number	US-9977075-B1
Application number	US-201615360899-A
Country	US
Kind code	B1
Filing date	Nov 23, 2016
Priority date	Nov 23, 2016
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

Embodiments detailed herein include an apparatus that includes a reliability assessment engine (RAE) stored in non-volatile memory and processing circuitry to execute the RAE to: receive data of at least one physical condition from a plurality of intra-die variation monitoring circuits, apply the received data least one to at least one reliability physics model, and calculate at least one of an estimated amount of lifetime consumed and an estimated amount of lifetime remaining.

First claim

What is claimed is:

1. An apparatus comprising:
a reliability assessment engine (RAE) stored in non-volatile memory; and
processing circuitry to execute the RAE to:
receive data of at least one physical condition from a plurality of intra-die variation monitoring circuits;
apply the received data to at least one reliability physics model, wherein the reliability physics model includes a time dependent dielectric breakdown model, a bias temperature stability model, an electromigration model, a negative/positive bias temperature model, an integrated reliability model, an edge damage monitor, a statistical model, and a fin-self-heat model;
calculate at least one of an estimated amount of lifetime consumed and an estimated amount of lifetime remaining based on the reliability physics model output; and
adjust an operation parameter based at least in part on the calculated amount of lifetime remaining.

2. The apparatus of claim 1 , wherein the statistical model comprises a Markov failure prediction model.

3. The apparatus of claim 1 , wherein the data of at least one physical condition sensed during a period of operation includes one or more sensed voltages, average of the one or more sensed voltages, one or more sensed temperatures, average of the one or more sensed temperatures, one or more workload measures, or average of the one or more workload measures.

4. The apparatus of claim 1 , wherein the RAE is part of power control circuitry.

5. The apparatus of claim 1 , wherein the RAE is to receive an indication of a desired performance state and adjust an operation parameter of an integrated circuit based at least in part on the received indication such that at least one of an average voltage, average temperature, or average workload metric is within a desired range.

6. The apparatus of claim 1 , further comprising:
a network interface communicatively coupled to the RAE to transmit and receive information to other RAEs.

7. The apparatus of claim 1 , wherein the RAE is to select a reliability physics model from the plurality of reliability physics models.

8. A method comprising:
receiving data representing at least one physical condition of an integrated circuit;
calculating an estimated amount of lifetime remaining of the integrated circuit using at least one on-die reliability physics model, wherein the reliability physics model includes a time dependent dielectric breakdown model, a bias temperature stability model, an electromigration model, a negative/positive bias temperature model, an integrated reliability model, an edge damage monitor, a statistical model, and a fin-self-heat model; and
adjusting an operating parameter of the integrated circuit based on the calculated estimated amount of lifetime remaining of the integrated circuit.

9. The method of claim 8 , wherein the statistical model comprises a Markov failure prediction model.

10. The method of claim 8 , wherein the data representing at least one physical condition includes one or more sensed voltages, average of the one or more sensed voltages, one or more sensed temperatures, average of the one or more sense temperatures, one or more workload measures, or average of the one or more workload measures.

11. The method of claim 8 , further comprising:
updating at least one of the on-die reliability physics models.

12. The method of claim 8 , wherein the operating parameter is adjusted such that at least one of an average voltage, average temperature, or average workload metric is within a desired range.

13. The method of claim 8 , further comprising:
calculating an estimated amount of lifetime consumed for the integrated circuit.

14. A method comprising:
receiving data representing at least one physical condition of an integrated circuit and a calculation related to a lifetime of the integrated circuit, wherein the calculation related to a lifetime of the integrated circuit is based on a reliability physics model and the reliability physics model is one or more of an edge damage monitor and a fin-self-heat model;
determining a desired performance state for the integrated circuit; and
transmitting information about the desired performance state to a die having the integrated circuit, whereby an operating parameter of the integrated circuit is adjusted to fit the desired performance state.

15. The method of claim 14 , the reliability physics model is one or more of a time dependent dielectric breakdown model, a bias temperature stability model, an electromigration model, a negative/positive bias temperature model, an integrated reliability model, a statistical model.

16. The method of claim 14 , wherein the data representing at least one physical condition includes one or more sensed voltages, average of the one or more sensed voltages, one or more sensed temperatures, average of the one or more sense temperatures, one or more workload measures, or average of the one or more workload measures.

Assignees

• Intel Corp

Inventors

• Connor Christopher F
• Querbach Bruce
• Mcfadden Gordon
• Khanna Rahul

Classifications

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G01R31/2858

  Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection · CPC title

• G01R31/2855 Primary

  Environmental, reliability or burn-in testing · CPC title

• G01R31/287

  Procedures; Software aspects · CPC title

• G01R31/2851 Primary

  Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801) · CPC title