Semiconductor structure and method for operating the same

Patent metadata

Field	Value
Publication number	US-9977072-B2
Application number	US-201514954566-A
Country	US
Kind code	B2
Filing date	Nov 30, 2015
Priority date	Nov 30, 2015
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

An integrated circuit (IC) and a method for operating the IC are provided. The IC comprises a device under test and a first heater. The first heater is located at a first side of the device and provides heat to control a temperature of the device. The first heater comprises a semiconductor device having a first doped region and a second doped region having a conductivity type opposite to that of the first doped region, the first doped region interfacing with the second doped region.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a device under test;
a first heater located at a first side of the device under test and providing heat to control a temperature of the device under test, wherein the first heater comprises a semiconductor device having a first doped region and a second doped region having a conductivity type opposite to that of the first doped region, the first doped region interfacing with the second doped region;
a first thermally conductively pad over the first heater;
a second thermally conductively pad located between the device under test and the first heater; and
a second set of thermally conductively pads surrounding the device under test, wherein the first thermally conductively pad and the second thermally conductively pad are connected with the second set of thermally conductively pads.

2. The integrated circuit of claim 1 , wherein the semiconductor device comprises a Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFET), a bipolar junction transistor (BJT) or a multi-gate non-planar field effect transistor (FinFET).

3. The integrated circuit of claim 1 , wherein the heat provided by the first heater is controlled based on a difference between a first voltage applied to the first doped region and a second voltage applied to the second doped region.

4. The integrated circuit of claim 2 , wherein the heat provided by the first heater is controlled based on the current flowing through a channel of the MOSFET, the BJT or the FinFET.

5. The integrated circuit of claim 1 , further comprising a second heater located at a second side of the device under test and providing heat to the device under test.

6. The integrated circuit of claim 1 , further comprising a second heater, a third heater and a fourth heater to surround the device under test and providing heat to the device under test.

7. The integrated circuit of claim 6 , wherein the first thermally conductively pad is over the second heater, the third heater and the fourth heater.

8. The integrated circuit of claim 7 , wherein the second set of thermally conductively pads, are further located between the device under test and the second heater, the device under test and the third heater, and the device under test and the fourth heater.

9. The integrated circuit of claim 1 , further comprising a sensor to detect the temperature of the device under test.

10. The integrated circuit of claim 9 , further comprising a temperature controller to receive the signal from the sensor and to control the heat generated by the first heater based on the received signal.

11. The semiconductor device of claim 1 , wherein the first thermally conductive pad is physically connected to the second set of thermally conductively pad.

12. A semiconductor device, comprising:
a device under test;
a first set of FinFETs located at a first side of the device under test to heat up the device under test, wherein the heat generated by the first set FinFETs is controlled by a power applied to each FinFETs;
one of a first set of thermally conductive pads located over the first set of FinFETs; and
one of a second set of thermally conductive pads located between the device under test and the first set of FinFETs.

13. The semiconductor device of claim 12 , further comprising a second set of FinFETs, a third set of FinFETs and a fourth set of FinFETs surrounding the device under test and to heat up the device under test.

14. The semiconductor device of claim 13 , wherein
the first set of thermally conductive pads further located over the second set of FinFETs, the third set of FinFETs and the fourth set of FinFETs; and
the second set of thermally conductive pads further located between the device under test and the second set of FinFETs, the device under test and the third set of FinFETs, and the device under test and the fourth set of FinFETs.

15. The semiconductor device of claim 12 , wherein the one of the first set of thermally conductive pads is physically connected to the one of the second set of thermally conductive pads.

16. A method for controlling a temperature of a device, comprising:
providing the device; and
arranging a first set of FinFETs at a first side of the device to heat up the device, wherein the heat generated by the first set FinFETs is controlled by a power applied to each FinFETs;
providing one of a first set of thermally conductive pads over the first set of FinFETs; and
providing one of a second set of thermally conductive pads between the device and the first set of FinFETs.

17. The method of claim 16 , further comprising arranging a second set of FinFETs, a third set of FinFETs and a fourth set of FinFETs to surround the device and to heat up the device.

18. The method of claim 17 , wherein
providing others of the first set of thermally conductive pads over the second set of FinFETs, the third set of FinFETs and the fourth set of FinFETs; and
providing others of the second set of thermally conductive pads between the device and the second set of FinFETs, the device and the third set of FinFETs, and the device and the fourth set of FinFETs.

19. The method of claim 16 , further comprising:
measuring a temperature of the device; and
increasing a power applied to each FinFET if the measured temperature is less than a predetermined value, or
decreasing a power applied to each FinFET if the measured temperature is higher than a predetermined value.

20. The semiconductor device of claim 16 , wherein the one of the first set of thermally conductive pads is physically connected to the one of the second set of thermally conductive pads.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Shih Jiaw-Ren
• Wang Jhong-Sheng
• Chen Shih-Hsin
• Lee Jen-Hao
• Huang Ting-Sheng

Classifications

• G01R31/2619

  for measuring thermal properties thereof · CPC title

• G01R31/2875

  related to heating · CPC title

• H10P74/27

  Structural arrangements therefor · CPC title

• G01R31/2628 Primary

  for measuring thermal properties thereof · CPC title

• H10W40/10 Primary

  Arrangements for heating · CPC title