Isolation circuits for digital communications and methods to provide isolation for digital communications

Patent metadata

Field	Value
Publication number	US-9973220-B2
Application number	US-201615166426-A
Country	US
Kind code	B2
Filing date	May 27, 2016
Priority date	Jun 30, 2014
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

Isolation circuits for digital communications and methods to provide isolation for digital communications are disclosed. An example isolation circuit includes an isolation barrier, a burst encoder in a first circuit, and an edge pattern detector in a second circuit. The example isolation barrier electrically isolates the first circuit from the second circuit. The example burst encoder generates a first pattern in response to receiving a rising edge on an input signal and generates a second pattern in response to receiving a falling edge on the input signal. The example edge pattern detector detects the first pattern or the second pattern received from the burst encoder via the isolation barrier, sets an output signal at a first signal level in response to detecting the first pattern, and sets the output signal at a second signal level in response to detecting the second pattern.

First claim

What is claimed is:

1. An isolation circuit, comprising:
an isolation barrier to electrically isolate a first circuit from a second circuit; a burst encoder in the first circuit, the burst encoder to:
generate a first pattern in response to receiving a rising edge on an input signal; and
generate a second pattern in response to receiving a falling edge on the input signal; and
an edge pattern detector in the second circuit, the edge pattern detector to:
detect the first pattern or the second pattern received from the burst encoder via the isolation barrier;
set an output signal at a first signal level in response to detecting the first pattern; and
set the output signal at a second signal level in response to detecting the second pattern;
wherein the burst encoder generates the first pattern by generating a first number of electrical pulses by outputting a first oscillating signal for a first time period;
wherein the burst encoder generates the second pattern by generating a second number of electrical pulses by outputting a second oscillating signal for the first time period, the second oscillating signal having a different frequency than the first oscillating signal.

2. The isolation circuit of claim 1 , in which the burst encoder is idle between generating instance of the first pattern and the second pattern.

3. The isolation circuit of claim 1 , in which the edge pattern detector is idle between detecting the first pattern and detecting the second pattern.

4. The isolation circuit of claim 1 , in which the burst encoder is to generate the second pattern by generating a second number of electrical pulses by outputting the first oscillating signal for a second time period.

5. The isolation circuit of claim 1 , further including an envelope detector in the second circuit, the envelope detector to reconstruct an envelope of the first pattern or the second pattern and provide an envelope signal including the first pattern or the second pattern to the edge pattern detector.

6. A method, comprising:
generating a first signal pattern in a first voltage domain in response to receiving a first rising edge on an input signal;
transmitting the first signal pattern to an electrical isolation barrier;
detecting the first signal pattern received in a second voltage domain via the electrical isolation barrier;
in response to detecting the first signal pattern, outputting a second rising edge on an output signal in the second voltage domain;
generating a second signal pattern in the first voltage domain in response to receiving a first falling edge on the input signal, the second signal pattern being different than the first signal pattern;
transmitting the second signal pattern to the electrical isolation barrier;
detecting the second signal pattern received in the second voltage domain via the electrical isolation barrier; and
in response to detecting the second signal pattern, outputting a second falling edge on the output signal in the second voltage domain.

7. The method of claim 6 , further including modulating the first signal pattern using a carrier signal, the transmitting the first signal pattern including transmitting the carrier signal containing the modulated first signal pattern.

8. The method of claim 7 , further including modulating the second signal pattern using the carrier signal, the transmitting the second signal pattern including transmitting the carrier signal containing the modulated second signal pattern.

9. The method of claim 6 , wherein the generating of the first signal pattern includes generating a first number of electrical pulses by using a first oscillating signal having a first frequency to output the first number of electrical pulses at the first frequency during a time period having a specified duration.

10. The method of claim 9 , wherein the detecting of the first signal pattern includes starting a timer and determining that a first number of pulses was received between the starting of the timer and receiving of a time out signal when the timer has finished counting.

Assignees

• Texas Instruments Inc

Inventors

• Kramer Bradley Allen
• Morgan Mark W
• Sankaran Swaminathan

Classifications

• H04L25/49

  using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels {; Baseband coding techniques specific to data transmission systems (spectral shaping H04L25/03828)} · CPC title

• H04L25/069

  by detecting edges or zero crossings · CPC title

• H04B2001/0408

  with power amplifiers · CPC title

• H04B1/0475 Primary

  with means for limiting noise, interference or distortion (H04B1/0483 takes precedence) · CPC title

• H04L25/0266 Primary

  Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling · CPC title