Semiconductor device

Patent metadata

Field	Value
Publication number	US-9973201-B2
Application number	US-201715654484-A
Country	US
Kind code	B2
Filing date	Jul 19, 2017
Priority date	Sep 23, 2016
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

According to one aspect, a semiconductor device ( 1 ) includes: an input circuit ( 11 _ 1 ) configured to receive an analog signal, the analog signal and a digital signal being selectively input; an input circuit ( 11 _ 4 ) configured to be driven by a power supply common to the input circuit ( 11 _ 1 ) and receive a digital signal, the digital signal and an analog signal being selectively input; an AD converter ( 15 ) configured to perform AD conversion of the analog signal input to the input circuit ( 11 _ 1 ); an edge detection circuit ( 12 ) configured to detect an edge of the digital signal input to the input circuit ( 11 _ 4 ); and a control unit ( 13 ) configured to execute predetermined processing on a result of the AD conversion by the AD converter ( 15 ) based on a result of the detection by the edge detection circuit ( 12 ).

First claim

What is claimed is:

1. A semiconductor device comprising:
a first input circuit configured to receive a first analog signal, the first analog signal and a first digital signal being selectively input;
a second input circuit configured to be driven by a power supply common to the first input circuit and receive a second digital signal, the second digital signal and a second analog signal being selectively input;
an AD converter configured to perform AD conversion of the first analog signal input to the first input circuit;
an edge detection circuit configured to detect an edge of the second digital signal input to the second input circuit; and
a control unit configured to execute predetermined processing on a result of the AD conversion by the AD conversion based on a result of the detection by the edge detection circuit.

2. The semiconductor device according to claim 1 , further comprising a third input circuit configured to be driven by the power supply common to the first input circuit and receive a third digital signal, the third digital signal and a third analog signal being selectively input,
wherein the edge detection circuit further detects an edge of the third digital signal input to the third input circuit, in addition to an edge of the second digital signal input to the second input circuit.

3. The semiconductor device according to claim 1 , wherein the control unit acquires a result of the AD conversion by the AD converter when no edge is detected by the edge detection circuit during the AD conversion by the AD converter.

4. The semiconductor device according to claim 3 , wherein the control unit does not acquire the result of the AD conversion by the AD converter when an edge is detected by the edge detection circuit during the AD conversion by the AD converter.

5. The semiconductor device according to claim 3 , further comprising:
a result storage unit configured to store the AD conversion result acquired by the control unit; and
a measurement unit configured to measure a period in which the AD conversion result is stored in the result storage unit.

6. The semiconductor device according to claim 1 , wherein the control unit acquires m (m is an integer equal to or greater than 2) successive AD conversion results obtained by the AD converter and averages the AD conversion results, and acquires, as reliability information, the number of times when an edge is detected by the edge detection circuit in the m times of AD conversion.

7. The semiconductor device according to claim 6 , further comprising:
a result storage unit configured to store the m AD conversion results acquired by the control unit and an average value of the m AD conversion results; and
a counter configured to count the number of times when an edge is detected by the edge detection circuit in the m times of AD conversion.

8. A semiconductor device comprising:
a first input circuit configured to receive an analog signal;
a second input circuit configured to be driven by a power supply common to the first input circuit and receive a digital signal;
an AD converter configured to perform AD conversion of the analog signal input to the first input circuit;
an edge detection circuit configured to detect an edge of the digital signal input to the second input circuit and output a detection result; and
a control unit configured to receive the detection result, and acquire a result of the AD conversion by the AD converter when the detection result indicates that no edge is detected by the edge detection circuit during the AD conversion by the AD converter.

9. The semiconductor device according to claim 8 , wherein the control unit does not acquire the result of the AD conversion by the AD converter when an edge is detected by the edge detection circuit during the AD conversion by the AD converter.

10. A semiconductor device comprising:
a first input circuit configured to receive an analog signal;
a second input circuit configured to be driven by a power supply common to the first input circuit and receive a digital signal;
an AD converter configured to perform AD conversion of the analog signal input to the first input circuit;
an edge detection circuit configured to detect an edge of the digital signal input to the second input circuit; and
a control unit configured to acquire m (m is an integer equal to or greater than 2) successive AD conversion results obtained by the AD converter and average the AD conversion results, and acquire, as reliability information, the number of times when an edge is detected by the edge detection circuit in the m times of AD conversion.

Assignees

• Renesas Electronics Corp

Inventors

• Yoshioka Yuki

Classifications

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H02M3/156

  with automatic control of output voltage or current, e.g. switching regulators · CPC title

• H03M1/462 Primary

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/0854 Primary

  of quantisation noise · CPC title