Local phase detection in realigned oscillator

Patent metadata

Field	Value
Publication number	US-9973195-B2
Application number	US-201514681239-A
Country	US
Kind code	B2
Filing date	Apr 8, 2015
Priority date	Apr 8, 2015
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

Representative implementations of devices and techniques provide reduced jitter and local phase detection for a controlled oscillator. An edge of a reference signal is injected at a point within the oscillator, and replaces an edge of the generated oscillation signal at the injection point. A phase difference of the injected reference signal and the oscillation signal is measured locally and is used to tune the oscillator.

First claim

What is claimed is:

1. A ring oscillator circuit, comprising:
a plurality of inverters coupled in series;
a plurality of multiplexers, each multiplexer of the plurality of multiplexers being coupled to an output of an inverter of the plurality of inverters at a first input of the multiplexer and coupled to an input of another inverter of the plurality of inverters at an output of the multiplexer, wherein each multiplexer of the plurality of multiplexers is arranged to receive a reference signal at a second input of the multiplexer and to output the reference signal when an enable signal received at the multiplexer is in a first state and to output an oscillation signal received at the first input of the multiplexer when the enable signal is in a second state; and
a phase detector coupled to the first input of a respective multiplexer of the plurality of multiplexers at a first input of the phase detector and coupled to the second input of the respective multiplexer at a second input of the phase detector.

2. The ring oscillator circuit of claim 1 , further comprising a charge pump and/or a loop filter coupled to an output of the phase detector and arranged to tune a frequency of the oscillation signal based on the output of the phase detector.

3. The ring oscillator circuit of claim 2 , wherein the phase detector is arranged to output an error signal to the charge pump and/or the loop filter, the charge pump and/or the loop filter increasing or decreasing a frequency of the oscillation signal based on the error signal.

4. The ring oscillator circuit of claim 1 , wherein the phase detector is arranged to measure a phase difference or a frequency difference between the oscillation signal and the reference signal at a predetermined point within the ring oscillator circuit and to output a difference signal based on the measuring.

5. The ring oscillator circuit of claim 1 , wherein the phase detector is located within a core of the oscillator circuit and is integral to the oscillator circuit.

6. The ring oscillator circuit of claim 1 , wherein the plurality of inverters and the plurality of multiplexers are arranged in a loop and generate the oscillation signal, and wherein the loop is opened at periodic intervals and an edge of the reference signal is replaced for an edge of the oscillation signal at the intervals.

7. The ring oscillator circuit of claim 6 , wherein the replacement of the edge of the reference signal for the edge of the oscillation signal adjusts a timing of the oscillation signal.

8. The ring oscillator circuit of claim 1 , wherein the reference signal comprises a periodic pulse signal having a rising edge and a falling edge on each pulse, one of the rising edge or the falling edge replacing an rising or falling edge of the oscillation signal at an output of a respective multiplexer of the plurality of multiplexers when the enable signal received at the respective multiplexer is in the first state.

9. A phase-locked loop (PLL) system, comprising:
a multi-stage ring oscillator circuit, including a plurality of multiplexers coupled to a plurality of inverters in a loop, the plurality of multiplexers coupled to the plurality of inverters such that a given multiplexer of the plurality of multiplexers is coupled to an output of a first respective inverter of the plurality of inverters at a first input of the given multiplexer and a second respective inverter of the plurality of inverters is coupled to an output of the given multiplexer at an input of the second respective inverter;
a phase detector coupled to the first input of a particular multiplexer of the plurality of multiplexers at a first input of the phase detector and to a second input of the particular multiplexer at a second input of the phase detector, the phase detector located within the multi-stage ring oscillator circuit; and
a control module arranged to enable the particular multiplexer via an enable signal according to a predetermined pattern, the particular multiplexer arranged to receive a reference signal at the second input of the particular multiplexer and to output the reference signal when the enable signal received at the particular multiplexer is in a first state and to output an oscillation signal received at the first input of the particular multiplexer when the enable signal is in a second state.

10. The PLL system of claim 9 , further comprising a loop filter and/or a charge pump arranged to receive an output from the phase detector and to tune a frequency of the multistage ring oscillator circuit based on the output from the phase detector.

11. The PLL system of claim 9 , further comprising a plurality of phase detectors coupled to the plurality of multiplexers, a given phase detector of the plurality of phase detectors coupled to a first input of a respective multiplexer of the plurality of multiplexers at a first input of the given phase detector and to a second input of the respective multiplexer at a second input of the given phase detector, the plurality of phase detectors arranged to detect a phase difference between an oscillation signal received at the first input of the given phase detector and a reference signal received at the second input of the given phase detector and to output a difference signal to the control module based on the detecting.

12. The PLL system of claim 9 , wherein the plurality of multiplexers are enabled at a frequency comprising a combination of an integer multiplication factor and a fractional multiplication factor of a frequency of the reference signal and in a predetermined pattern.

13. The PLL system of claim 9 , wherein the particular multiplexer is arranged to replace an edge of the reference signal for an edge of the oscillation signal when the second input of the particular multiplexer is selected via the enable signal.

14. The PLL system of claim 9 , wherein the control module is arranged to realign a phase and/or a frequency of the oscillation signal by enabling the particular multiplexer and injecting an edge of the reference signal into the particular multiplexer during a time window encompassing an edge of the oscillation signal, the edge of the reference signal replacing the edge of the oscillation signal during the time window.

15. The PLL system of claim 14 , wherein the control module is arranged to match a timing delay between an injected reference signal at the second input of the particular multiplexer and the oscillation signal at the first input of the particular multiplexer.

16. The PLL system of claim 9 , wherein the multi-stage ring oscillator circuit comprises a digitally controlled ring oscillator (DCRO) or an analog voltage controlled oscillator (VCO).

17. A method, comprising:
alternately coupling a plurality of multiplexers to a plurality of inverters such that a given multiplexer of the plurality of multiplexers is coupled to an output of a first respective inverter of the plurality of inverters at a first input of the given multiplexer and a second respective inverter of the plurality of inverters is coupled to an output of the given multiplexer at an input of the second respective inverter;
receiving, by each multiplexer of the plurality of multiplexers, a reference signal such that the reference signal is received at a second input of a given multiplexer of the plurality of multiplexers;
outputting, from each multiplexer of the plurality of multiplexers, the reference signal when an enable signal received at a given multiplexer of the plurality of multiplexers is in a first state;
outputting, from each multiplexer of the pluralit

Assignees

• Infineon Technologies Ag

Inventors

• Grollitsch Werner
• VITRENKO Oleg

Classifications

• H03L7/087 Primary

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H03L7/0997

  Controlling the number of delay elements connected in series in the ring oscillator · CPC title

• H03L7/083

  the reference signal being additionally directly applied to the generator · CPC title

• H03L7/0995

  the oscillator comprising a ring oscillator · CPC title