Current-limiting in an amplifier system

Patent metadata

Field	Value
Publication number	US-9973152-B2
Application number	US-201615350773-A
Country	US
Kind code	B2
Filing date	Nov 14, 2016
Priority date	May 1, 2014
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

One example includes an amplifier system. The system includes a gain stage configured to conduct a gain current in response to an input voltage. The system also includes a current limit stage coupled to the gain stage and being configured to one of source and sink the gain current and to define a limit amplitude of the gain current during a current limit condition. The system further includes an output stage coupled to the gain stage and configured to conduct an output current through an output node in response to the gain current, the output current having a maximum amplitude during the current limit condition that is proportional to the limit amplitude.

First claim

The invention claimed is:

1. An amplifier system comprising:
a gain stage configured to conduct a gain current in response to an input voltage;
a current limit stage coupled to the gain stage and being configured to one of source and sink the gain current and to define a limit amplitude of the gain current during a current limit condition, wherein the current limit stage comprises a first transistor and a second transistor being arranged as a current mirror and a current source, wherein a predetermined current is provided from the current source through the first transistor, and wherein the second transistor is configured to one of source and sink the gain current based on the predetermined current through the first transistor; and
an output stage coupled to the gain stage and configured to conduct an output current through an output node in response to the gain current, the output current having a maximum amplitude during the current limit condition that is proportional to the limit amplitude.

2. An amplifier system comprising:
a gain stage configured to conduct a gain current in response to a differential input voltage, the differential input voltage comprising a first input voltage and a second input voltage; and
a current limit stage coupled to the gain stage and being configured to one of source and sink the gain current and to define a limit amplitude of the gain current during a current limit condition, wherein the current limit stage comprises:
a first current limit stage configured to source the gain current through the gain stage based on a negative difference between the first input voltage and the second input voltage; and
a second current limit stage configured to sink the gain current through the gain stage based on a positive difference between the first input voltage and the second input voltage, the system further comprising:

an output stage coupled to the gain stage and configured to conduct an output current through an output node in response to the gain current, the output current having a maximum amplitude during the current limit condition that is proportional to the limit amplitude.

3. The system of claim 1 , wherein the output stage comprises a source-follower arrangement of transistors, such that the output stage one of sources and sinks the output current provided out from or into the output node during a current limit condition.

4. An amplifier system comprising:
a gain stage configured to conduct a gain current in response to an input voltage, wherein the gain stage comprises a plurality of transistors that are configured as a cross-coupled transistor arrangement configured to sink the gain current through a first pair of transistors of the cross-coupled transistor arrangement during a sinking current limit condition and to source the gain current through a second pair of transistors of the cross-coupled transistor arrangement during a sourcing current limit condition;
a current limit stage coupled to the gain stage and being configured to one of source and sink the gain current and to define a limit amplitude of the gain current during a current limit condition; and
an output stage coupled to the gain stage and configured to conduct an output current through an output node in response to the gain current, the output current having a maximum amplitude during the current limit condition that is proportional to the limit amplitude.

5. The system of claim 4 , wherein a first transistor of the first pair of transistors and a first transistor of the second pair of transistors are controlled by respective predetermined reference voltages, and wherein a second transistor of the first pair of transistors and a second transistor of the second pair of transistors are controlled by the input voltage.

6. The system of claim 5 , further comprising a reference stage coupled to the first transistor of the first pair of transistors and the first transistor of the second pair of transistors as respective current mirrors, the reference stage being configured to set a magnitude of the predetermined reference voltages based on a reference current.

7. The system of claim 6 , wherein the input voltage is a differential voltage comprising a first input voltage and a second input voltage, the system further comprising:
a first control node associated with the first input voltage and being coupled to a source of a first reference transistor that is controlled via a second of the predetermined reference voltages; and
a second control node associated with the second input voltage and being coupled to a source of a second reference transistor that is controlled via the second of the predetermined reference voltages;
wherein the second transistor of the first pair of transistors is controlled via activation of the first reference transistor in response to the first input voltage and the second transistor of the second pair of transistors is controlled via activation of the second reference transistor in response to the second input voltage.

8. The system of claim 4 , wherein the gain stage is a first gain stage, the system further comprising a second gain stage comprising a first gain stage current mirror and a second gain stage current mirror, wherein a first transistor of the first pair of transistors is coupled to the first gain stage current mirror and a first transistor of the second pair of transistors is coupled to the second gain stage current mirror, wherein the output stage is coupled to the first gain stage current mirror and the second gain stage current mirror, such that the gain current controls the magnitude of the output current via the respective first and second gain stage current mirrors.

9. The system of claim 8 , wherein the output stage comprises a first output transistor, a second output transistor, an output control transistor, and a diode, wherein the first output transistor and the output control transistor are arranged in a source-follower configuration, wherein the first output transistor and the output control transistor are configured to conduct the output current to flow from the output node in response to the sourcing current limit condition, and wherein the second output transistor and the diode are configured to conduct the output current that is provided from the output node in response to the sinking current limit condition.

10. A voltage amplifier system comprising:
a gain stage comprising a plurality of transistors configured to conduct at least one of a sinking current and a sourcing current in response to an input voltage, wherein the plurality of transistors are configured as a cross-coupled transistor arrangement configured to conduct the sinking current through a first pair of transistors of the cross-coupled transistor arrangement during a sinking current limit condition and to conduct the sourcing current through a second pair of transistors of the cross-coupled transistor arrangement during a sourcing current limit condition;
at least one current limit stage comprising a current mirror configured to provide the at least one of the sinking current and the sourcing current and to define a limit amplitude of the at least one of the sinking current and the sourcing current during a current limit condition; and
an output stage coupled to the gain stage and configured to conduct an output current through an output node in response to the at least one of the sinking current and the sourcing current to provide an output voltage at the output node, the output current having a maximum amplitude during the current limit condition that is proportional to the limit amplitude.

11. The system of claim 10 , wherein a first transistor of the first pair of transisto

Assignees

• Texas Instruments Inc

Inventors

• Otani Daijiro
• Ikai Keita

Classifications

• G11B5/48

  Disposition or mounting of heads {or head supports} relative to record carriers {(mounting of head within housing G11B5/105); arrangements of heads, e.g. for scanning the record carrier to increase the relative speed (driving of both record carriers and head G11B15/18; guiding record carriers G11B15/60; head selecting circuits G11B15/12)} · CPC title

• G11B5/59622

  Gain control; Filters · CPC title

• H03F3/303

  using opamps as driving stages · CPC title

• G11B5/596

  for track following on disks {(G11B5/5526, G11B5/5552, G11B5/5565, G11B5/5582 take precedence)} · CPC title

• H03F2200/426

  the amplifier comprising circuitry for protection against overload · CPC title