Semiconductor devices

Patent metadata

Field	Value
Publication number	US-9972716-B2
Application number	US-201514826439-A
Country	US
Kind code	B2
Filing date	Aug 14, 2015
Priority date	Aug 14, 2014
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

Provided are semiconductor devices that include an active pattern on a substrate, first and second gate electrodes on the active pattern and arranged in a first direction relative to one another and a first source/drain region in a first trench that extends into the active pattern between the first and second gate electrodes. The first source/drain region includes a first epitaxial layer that is configured to fill the first trench and that includes at least one plane defect that originates at a top portion of the first epitaxial layer and extends towards a bottom portion of the first epitaxial layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
an active pattern on a substrate;
first and second gate electrodes on the active pattern and arranged in a first direction relative to one another;
a first source/drain region in a first trench that extends into the active pattern between the first and second gate electrodes, the first source/drain region including a first epitaxial layer in the first trench that includes a first plane defect that originates at a first origination location that is at a top portion of the first epitaxial layer and that extends towards a bottom portion of the first epitaxial layer, a second plane defect that originates at a second origination location that is at the top portion of the first epitaxial layer and that extends towards the bottom portion of the first epitaxial layer; and
first and second gate spacers on sidewalls of the first and second gate electrodes, respectively
wherein the first gate spacer overlaps the first origination location of the first plane defect in a third direction that extends away from the substrate,
wherein the first plane defect and the second plane defect are symmetrical with respect to a center of the first epitaxial layer and are completely located within the first epitaxial layer and are non-intersecting,
wherein the first origination location is positioned at a boundary surface between the first gate spacer and the first epitaxial layer, and
wherein a portion of the first epitaxial layer is disposed between a bottom surface of the first gate spacer and the first plane defect at the first origination location, and between a bottom surface of the second gate spacer and the second plane defect at the second origination location.

2. The semiconductor device according to claim 1 , wherein the first and second gate spacers comprise a portion that extends beyond a sidewall of the first trench to have a first distance between the first and second gate spacers that is less than a second distance between opposite sidewalls of the first trench.

3. The semiconductor device according to claim 1 , wherein the first epitaxial layer comprises:
a first lower epitaxial layer that is on at least a portion of a bottom surface of the first trench;
a first upper epitaxial layer that is on the first lower epitaxial layer; and
a first capping epitaxial layer that is on the first upper epitaxial layer.

4. The semiconductor device according to claim 1 , wherein the first plane defect and the second plane defect each extend towards one another at an angle relative to a top surface of the active pattern.

5. The semiconductor device according to claim 1 ,
wherein the first plane defect is overlapped by the first gate spacer in the third direction that extends away from the substrate at a first upper portion of the first plane defect that is nearest the first gate spacer, and
wherein the second plane defect is overlapped by the second gate spacer in the third direction at a second upper portion of the second plane defect that is nearest the second gate spacer.

6. The semiconductor device according to claim 1 , wherein the first epitaxial layer comprises:
a first lower epitaxial layer that is on at least a portion of a bottom surface of the first trench; and
a first upper epitaxial layer that is on the first lower epitaxial layer, and
wherein the first plane defect and the second plane defect propagate from the first upper epitaxial layer and terminate within the first upper epitaxial layer.

7. The semiconductor device according to claim 1 , wherein a height of the first plane defect from the active pattern increases as a distance from the first gate electrode decreases.

8. The semiconductor device according to claim 1 , wherein a width of the first plane defect decreases as a distance to the first gate electrode decreases.

9. The semiconductor device according to claim 1 , wherein the first epitaxial layer comprises:
a first lower epitaxial layer that is on at least a portion of a bottom surface of the first trench; and
a first upper epitaxial layer that is on the first lower epitaxial layer, and
wherein the first lower epitaxial layer contacts a bottom surface of each of the first and second gate spacers.

10. The semiconductor device according to claim 9 ,
wherein the first and second plane defects propagate from the first lower epitaxial layer and terminate in the first upper epitaxial layer.

11. The semiconductor device according to claim 1 ,
wherein the active pattern comprises a fin-type active pattern extending from a top surface of the substrate and extending in the first direction, and
wherein the first and second gate electrodes extend across the fin-type active pattern in a second direction that is different from the first direction.

12. The semiconductor device according to claim 11 ,
wherein the first epitaxial layer comprises:
a first lower epitaxial layer that is on at least a portion of a bottom surface of the first trench;
a first upper epitaxial layer that is on the first lower epitaxial layer; and
a first capping epitaxial layer that is on the first upper epitaxial layer,
wherein the fin-type active pattern comprises a first fin-type active pattern, the semiconductor device further comprising a second fin-type active pattern extending from the top surface of the substrate and in the first direction and spaced apart from the first fin-type active pattern in the second direction,
wherein the first and second gate electrodes are on and extend across the second fin-type active pattern in the second direction,
the semiconductor device further comprising a second source/drain region in a second trench that extends into the second fin-type active pattern between the first and second gate electrodes, the second source/drain region including a second epitaxial layer that is in the second trench and that includes at least one plane defect that is terminated within the second epitaxial layer.

13. The semiconductor device according to claim 12 , wherein the second epitaxial layer comprises:
a second lower epitaxial layer that is on at least a portion of a bottom surface of the second trench in the second fin-type active pattern;
a second upper epitaxial layer that is on the second lower epitaxial layer; and
a second capping epitaxial layer that is on the second upper epitaxial layer, and
wherein the first capping epitaxial layer is directly connected to the second capping epitaxial layer.

14. The semiconductor device according to claim 1 ,
wherein the active pattern comprises a fin-type active pattern extending from a top surface of the substrate and extending in the first direction,
wherein the first and second gate electrodes extend across the fin-type active pattern in a second direction that is different from the first direction, and
wherein the first trench is on a first side of the first gate electrode,
the semiconductor device further comprising a second source/drain region in a second trench that extends into the active pattern on a second side of the first gate electrode, the second source/drain region including a second epitaxial layer that is in the second trench and that includes a third plane defect that originates at a top portion of the second epitaxial layer proximate the first gate electrode and extends towards a bottom portion of the second epitaxial layer.

15. The semiconductor device according to claim 14 , further comprising a dummy gate electrode that extends across the fin-type active pattern in the second direction and is arranged in the first direction relative to the first and second gat

Assignees

• Kim Jin Bum
• Kim Seok Hoon
• Kim Chul
• Lee Kwan Heum
• Lee Byeong Chan
• Lee Cho Eun
• Jung Su Jin
• Koo Bon Young
• Samsung Electronics Co Ltd

Inventors

• Kim Jin-Bum
• Kim Seok-Hoon
• Kim Chul
• Lee Kwan-Heum
• Lee Byeong-Chan
• Lee Cho-Eun
• Jung Su-Jin
• Koo Bon-Young

Classifications

• H10P36/03

  within silicon bodies · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H01L29/7848 Primary

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic