Method for producing a dielectric field plate in a substrate trench, a corresponding substrate, and a power transistor

Patent metadata

Field	Value
Publication number	US-9972690-B2
Application number	US-201515300524-A
Country	US
Kind code	B2
Filing date	Mar 9, 2015
Priority date	Apr 3, 2014
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

A substrate includes a trench with walls and a base. The substrate also includes a dielectric field plate. The dielectric field plate consists of at least one first dielectric layer, which only adjoins lower sections of the walls of the trench and the base of the trench. Parasitic capacitances can be reduced when using this substrate for power transistors.

First claim

The invention claimed is:

1. A method for producing a dielectric field plate in a trench of a substrate, comprising:
depositing a dielectric structure onto walls and a floor of the trench and onto surface sections of the substrate which are adjacent to the trench, wherein a material or materials of the substrate includes a silicon carbide layer that forms the floor and lower sections of the walls, and wherein a dielectric material or dielectric materials which are included in the dielectric structure differ from the material or materials of the substrate;
depositing a stop material which fills the trench, covers the dielectric structure, and is different from the dielectric material or the dielectric materials, wherein the stop material is also different from a material or materials of the substrate;
selective etching back of a portion of the stop material with a first etching mechanism such that a portion of the dielectric structure which covers the surface sections of the substrate and the walls of the trench is exposed;
selective etching back of the dielectric structure with a second etching mechanism which is different from the first etching mechanism such that the surface of the substrate and upper sections of the walls are exposed, wherein a remainder of the dielectric structure, which covers the floor and the lower sections of the walls, remains; and
selective etching back of a remainder of the stop material with a third etching mechanism which is different from the second etching mechanism.

2. The method as claimed in claim 1 , wherein the dielectric material is selected from a material group including silicon dioxide, silicon nitride, aluminum oxide, intrinsic polysilicon carbide, and thermally oxidized polysilicon.

3. The method as claimed in claim 1 , wherein the stop material is selected from a material group including dielectrics, semiconductors, or metals.

4. The method as claimed in claim 1 , wherein the trench and the remainder of the dielectric structure are U-shaped.

5. The method as claimed in claim 1 , wherein the first etching mechanism and the third etching mechanism are identical.

6. A substrate, comprising:
a trench including walls and a floor;
a first dielectric layer disposed entirely on the surfaces of the walls and the floor;
a second dielectric layer disposed entirely on the surfaces of the first dielectric layer; and
a dielectric field plate comprising a third dielectric layer that is disposed on the second dielectric layer,
wherein the dielectric field plate abuts only portions of the second dielectric layer corresponding to lower sections of the walls of the trench and the floor of the trench.

7. The substrate as claimed in claim 6 , wherein:
the substrate further includes a silicon carbide layer and a p-doped silicon carbide layer which is arranged directly on the silicon carbide layer;
the trench extends through the p-doped silicon carbide layer into the silicon carbide layer; and
the silicon carbide layer defines the floor and lower sections of the walls of the trench.

8. A power transistor, comprising:
a substrate, including:
a trench including walls and a floor;
a first dielectric layer disposed entirely on the surfaces of the walls and the floor;
a second dielectric layer disposed entirely on the surfaces of the first dielectric layer; and
a dielectric field plate comprising a third dielectric layer that is disposed on the second dielectric layer,
wherein the dielectric field plate abuts only portions of the second dielectric layer corresponding to lower sections of the walls of the trench and the floor of the trench; and

a gate electrode disposed on the dielectric field plate.

9. The power transistor as claimed in claim 8 , wherein the second dielectric material is selected from the material group including silicon dioxide, silicon nitride, aluminum oxide, intrinsic polysilicon carbide, and thermally oxidized polysilicon.

10. The power transistor as claimed in claim 8 , wherein the dielectric field plate surrounds the gate electrode only in a region of the trench within a silicon carbide layer of the substrate.

Assignees

• Bosch Gmbh Robert

Inventors

• Trautmann Achim
• Banzhaf Christian Tobias

Classifications

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D12/038

  having a recessed gate, e.g. trench-gate IGBTs · CPC title

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H01L29/66734

  Electricity · mapped topic

• H01L29/7813

  Electricity · mapped topic