Low-K dielectric spacer for a gate cut

Patent metadata

Field	Value
Publication number	US-9972495-B1
Application number	US-201615387984-A
Country	US
Kind code	B1
Filing date	Dec 22, 2016
Priority date	Dec 22, 2016
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

Structures including one or more field-effect transistors and methods for forming a structure that includes one or more field-effect transistors. A first semiconductor fin and a second semiconductor fin are formed in which the second semiconductor fin is spaced from the first semiconductor fin. A semiconductor layer is formed that covers the first semiconductor fin and the second semiconductor fin. An opening is formed in the semiconductor layer that exposes the first semiconductor fin. A dielectric spacer is formed on at least one sidewall of the semiconductor layer bordering the opening.

First claim

What is claimed is:

1. A method comprising:
forming a first semiconductor fin and a second semiconductor fin spaced from the first semiconductor fin;
forming a first semiconductor layer that covers the first semiconductor fin and the second semiconductor fin;
forming an opening in the first semiconductor layer that exposes the first semiconductor fin;
forming a dielectric spacer on at least one sidewall of the first semiconductor layer bordering the opening;
forming a second semiconductor layer that fills the opening and covers the first semiconductor fin; and
patterning the first semiconductor layer and the second semiconductor layer to respectively form a first section and a second section of a dummy gate structure,
wherein the dielectric spacer includes a section located between the first section of the dummy gate structure and the second section of the dummy gate structure.

2. The method of claim 1 wherein the dielectric spacer is comprised of a low-k dielectric material.

3. The method of claim 1 wherein the dielectric spacer is comprised of silicon boron carbide nitride (SiBCN), silicon oxycarbonitride (SiOCN), or silicon carbonitride (SiCN).

4. The method of claim 1 wherein the at least one sidewall of the opening is located horizontally between the first semiconductor fin and the second semiconductor fin.

5. The method of claim 1
wherein the dielectric spacer is patterned when the first section of the dummy gate structure and the second section of the dummy gate structure are patterned.

6. The method of claim 5 further comprising:
replacing the first section of the dummy gate structure with a first functional gate structure; and
replacing the second section of the dummy gate structure with a second functional gate structure,
wherein the section of the dielectric spacer is located between the first functional gate structure and the second functional gate structure, and the section of the dielectric spacer electrically isolates the first functional gate structure from the second functional gate structure.

7. The method of claim 6 wherein the first functional gate structure extends across the first semiconductor fin, and the second functional gate structure extends across the second semiconductor fin.

8. The method of claim 6 wherein the first functional gate structure directly contacts the section of the dielectric spacer, and the second functional gate structure directly contacts the section of the dielectric spacer.

9. The method of claim 1 wherein forming the opening in the first semiconductor layer that exposes the first semiconductor fin comprises:
selectively removing the first semiconductor layer with a first etching process to form the opening.

10. The method of claim 9 further comprising:
forming a patterned hardmask layer on the first semiconductor layer,
wherein the patterned hardmask layer masks the first semiconductor layer outside of the opening during the first etching process.

11. The method of claim 10 wherein forming the dielectric spacer on the at least one sidewall of the opening comprises:
depositing a conformal layer of dielectric material on the at least one sidewall and the first semiconductor fin; and
removing the dielectric material of the conformal layer from the first semiconductor fin selective to the patterned hardmask layer with a second etching process that is anisotropic.

12. The method of claim 9 wherein the first semiconductor fin is covered by a dielectric layer, and the first semiconductor layer is removed selective to the dielectric layer by the first etching process.

13. The method of claim 1 wherein forming the dielectric spacer on the at least one sidewall of the opening comprises:
depositing a conformal layer of dielectric material on the at least one sidewall and the first semiconductor fin; and
anisotropically etching the dielectric material of the conformal layer to form the dielectric spacer.

14. The method of claim 1 wherein the dielectric spacer is located horizontally between the first semiconductor fin and the second semiconductor fin.

15. The method of claim 1 wherein the dielectric spacer has a thickness that is less than or equal to 10 nanometers.

Assignees

• Globalfoundries Inc

Inventors

• Wu Xusheng

Classifications

• H10D64/01326 Primary

  Aspects related to lithography, isolation or planarisation of the conductor · CPC title

• H01L21/823431

  Electricity · mapped topic

• H01L21/28123 Primary

  Electricity · mapped topic

• H01L27/0886

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic