Method of reducing defects in an epitaxial layer

Patent metadata

Field	Value
Publication number	US-9972488-B2
Application number	US-201615066262-A
Country	US
Kind code	B2
Filing date	Mar 10, 2016
Priority date	Mar 10, 2016
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

A method of reducing defects in an epitaxial layer. The method includes forming one or more barrier structures within a peripheral edge region of a wafer substrate, and forming an epitaxial layer over a surface of the wafer substrate.

First claim

What is claimed is:

1. A method, comprising:
forming one or more edge defect termination structures around an edge of a substrate that are between the edge and an interior region of the substrate and within a peripheral edge region of the substrate, wherein the one or more edge defect termination structures include one or more trenches that each have a depth below a surface of the substrate and a sidewall facing the edge of the substrate that provides a barrier between the sidewall and the edge that prevents dislocation defects that originate between the sidewall and the edge from continuing to the interior region of the substrate; and
forming an epitaxial layer over a surface of the substrate.

2. The method of claim 1 , wherein the epitaxial layer comprises a material selected from a group of materials consisting of Si, Ge, GaN, SiC and any combination of these materials.

3. The method of claim 1 , wherein the epitaxial layer has a thickness that is between 5 microns and 200 microns, inclusive.

4. The method of claim 1 , wherein the peripheral edge region has a width that is between 100 microns and 7 millimeters, inclusive.

5. The method of claim 1 , wherein the substrate comprises a material selected from a group of materials consisting of Si, SiC, GaN, SiGe, SOI, GaAs and any combination of these materials.

6. The method of claim 1 , wherein forming the epitaxial layer over the surface of the substrate comprises filling at least a portion of the one or more trenches with the epitaxial layer.

7. The method of claim 1 , further comprising filling the one or more trenches with a material selected from a group of materials consisting of Si 3 N 4 , SiC, SiON, SiO 2 , Ta 2 O 5 , ZrO 2 , Al 2 O 3 , polysilicon, amorphous silicon, semi-insulating polysilicon, amorphous carbon and any combination of these materials.

8. The method of claim 1 , further comprising filling the one or more trenches with a material having a thermal conductivity that is greater than the thermal conductivity of the substrate.

9. The method of claim 1 , wherein forming the one or more edge defect termination structures further comprises covering the one or more trenches using a Venecia process to define one or more cavities within the substrate.

10. The method of claim 1 , wherein forming the one or more edge defect termination structures further comprises:
filling at least a portion of the one or more trenches with a material selected from a group of materials consisting of Si 3 N 4 , SiC, SiON, SiO 2 , Ta 2 O 5 , ZrO 2 , Al 2 O 3 , polysilicon, amorphous silicon, semi-insulating polysilicon, amorphous carbon and any combination of these materials; and
covering the one or more trenches using a Venecia process.

11. The method of claim 1 , wherein forming the one or more edge defect termination structures comprises forming one or more oxide structures on a top surface of the substrate and not within the one or more trenches, and wherein forming the epitaxial layer comprises forming the epitaxial layer over the one or more oxide structures.

12. The method of claim 1 , wherein forming the one or more edge defect termination structures comprises forming one or more oxide structures on a top surface of the substrate and not within the one or more trenches, and wherein forming an epitaxial layer comprises forming a polycrystalline layer over the one or more oxide structures.

13. A method for reducing defects during epitaxial deposition, comprising:
providing a crystalline wafer substrate;
forming one or more edge defect termination structures around an edge of the wafer substrate that are between the edge and an interior region of the wafer substrate and within a peripheral edge region of the wafer substrate, wherein the one or more edge defect termination structures include one or more trenches that each have a depth below a surface of the wafer substrate and a sidewall facing the edge of the wafer substrate that is nonparallel to the surface that provides a barrier between the sidewall and the edge that prevents dislocation defects that originate between the sidewall and the edge from continuing to the interior region of the wafer substrate; and
depositing an epitaxial layer over the surface of the wafer substrate.

14. The method of claim 13 , wherein the wafer substrate comprises a material selected from a group of materials consisting of Si, SiC, GaN SiGe, SOT, GaAs and any combination of these materials.

15. The method of claim 13 , further comprising filling the one or more trenches with a material selected from a group of materials consisting of Si 3 N 4 , SiC, SiON, SiO 2 , Ta 2 O 5 , ZrO 2 , Al 2 O 3 , polysilicon, amorphous silicon, semi-insulating polysilicon, amorphous carbon and any combination of these materials.

16. The method of claim 13 , wherein forming the one or more edge defect termination structures further comprises covering the one or more trenches using a Venecia process to define one or more cavities within the wafer substrate.

17. The method of claim 13 , wherein forming the one or more edge defect termination structures comprises forming one or more oxide structures on a top surface of the wafer substrate and not within the one or more trenches, and wherein forming the epitaxial layer comprises forming the epitaxial layer over the one or more oxide structures.

18. The method of claim 17 , wherein the one or more oxide structures comprise a material selected from a group of materials consisting of SiO 2 , SiON, Ta 2 O 5 , Al 2 O 3 , Ga 2 O 3 , In 2 O 3 , SnO 2 , TiO 2 , amorphous carbon, graphite, diamond-like carbon and any combination of these materials.

Assignees

• Infineon Technologies Ag

Inventors

• Schulze Hans-Joachim
• Oefner Helmut
• Baumgartl Johannes

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2921

  being crystalline insulating materials · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H10P14/36

  characterised by treatments done before the formation of the materials · CPC title

• H10P14/2925 Primary

  Surface structures · CPC title