Memory buffer with data scrambling and error correction

Patent metadata

Field	Value
Publication number	US-9972369-B2
Application number	US-201514923345-A
Country	US
Kind code	B2
Filing date	Oct 26, 2015
Priority date	Apr 11, 2011
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

A method for operating a DRAM device. The method includes receiving in a memory buffer in a first memory module hosted by a computing system, a request for data stored in RAM of the first memory module from a host controller of the computing system. The method includes receiving with the memory buffer, the data associated with a RAM, in response to the request and formatting with the memory buffer, the data into a scrambled data in response to a pseudo-random process. The method includes initiating with the memory buffer, transfer of the scrambled data into an interface device.

First claim

We claim:

1. A method for operating a server system, the method comprising:
providing a server system, including a host controller device operably coupled to a Dynamic Random Access Memory (DRAM) device;
receiving in a first memory buffer in a memory module comprising a first Dual Inline Memory Module (DIMM) hosted by a computing system, a first request to store a data word;
in response to the first request, the first memory buffer striping the data word across the first DIMM and a second Dual Inline Memory Module (DIMM), such that loading on any byte lane of the first DIMM is limited to an electrical load;
receiving in the first memory buffer a second request for the data word stored in part in a Random Access Memory (RAM) of the memory module from a host controller of the computing system, the request comprising address signals;
the first memory buffer decoding the address signals and initiating a first rank decode function in response to a single chip select signal received from host controller;
a second memory buffer of the second DIMM initiating a second rank decode function in response to the single chip select signal;
receiving with the first memory buffer, part of the data word associated with a second RAM of the second DIMM, in response to the request;
formatting with the first memory buffer, the data word into a scrambled data word in response to a pseudo-random process; and
initiating with the memory buffer, transfer of the scrambled data word into an interface device.

2. The method of claim 1 further comprising formatting the data word with an error correction code; wherein the electrical load is two electrical loads.

3. The method of claim 1 , the scrambled data word using at least a state information comprising at least one of an address, a bank, and address/bank.

4. The method of claim 1 further comprising subjecting the data word to an error correction code (ECC).

5. The method of claim 1 further comprising subjecting the data word to an error correction code (ECC) characterized by a programmable ECC polynomial configured across the interface or a portion of the interface.

6. The method of claim 1 wherein the interface is configured to either a separate memory, a server, or other storage device.

7. The method of claim 1 further comprising a Cyclic Redundancy Check (CRC) correction to the data word.

8. The method of claim 1 further comprising a Cyclic Redundancy Check (CRC) correction and an error correction code (ECC) across the interface.

9. A method for operating a server system, the method comprising:
in a server system comprising a host controller coupled to a Dynamic Random Access Memory (DRAM) device;
receiving in a first memory buffer in a memory module comprising a first Dual Inline Memory Module (DIMM) hosted by a computing system, a request for a data word stored in part in a first Random Access Memory (RAM) of the memory module such that loading on any byte lane of the first DIMM is limited to an electrical load, the request received from a host controller of the computing system, the request comprising address signals and a single chip select signal;
the first memory buffer decoding the address signals and initiating a first rank decode function in response to the single chip select signal;
a second memory buffer of the second Dual Inline Memory Module (DIMM) on which a remaining part of the data word is stored, initiating a second rank decode function in response to the single chip select signal;
receiving with the first memory buffer, the remaining part of the data word associated with a second Random Access Memory (RAM) of the second DIMM, in response to the request;
formatting with the first memory buffer, the data word into a scrambled data word in response to a pseudo-random process; and
initiating with the first memory buffer, transfer of the scrambled data word into an interface device; and
maintaining an error correction code (ECC) on the interface device concurrent with the scrambled data word.

10. The method of claim 9 further comprising formatting the scrambled data word with an error correction code.

11. The method of claim 9 , the scrambled data word using at least a state information comprising at least one of an address, a bank, and address/bank.

12. The method of claim 9 wherein the data word is subjected to an error correction code (ECC).

13. The method of claim 9 wherein the error correction code (ECC) is characterized by a programmable ECC polynomial configured across the interface or a portion of the interface.

14. The method of claim 9 wherein the interface is configured to either a separate memory, a server, or other storage device.

15. The method of claim 9 further comprising a Cyclic Redundancy Check (CRC) correction to the data word.

Assignees

• Rambus Inc

Inventors

• Haywood Christopher
• Wang David

Classifications

• G11C7/1072 Primary

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• G06F11/1008

  in individual solid state devices (G06F11/1004 takes precedence) · CPC title

• G06F11/0778

  Dumping, i.e. gathering error/state information after a fault for later diagnosis · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C2029/0411

  Online error correction · CPC title