Integrated circuit authentication

Patent metadata

Field	Value
Publication number	US-9970986-B2
Application number	US-201514640180-A
Country	US
Kind code	B2
Filing date	Mar 6, 2015
Priority date	Mar 11, 2014
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

Systems and methods for authenticating integrated circuits. An example integrated circuit may comprise: a plurality of functional units electrically coupled to a power source; and an authenticating circuit comprising a plurality of voltage measurement units, each voltage measurement unit to measure, at one or more frequencies over one or more periods of time, a local voltage at a respective functional unit of the plurality of functional units.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a plurality of functional units electrically coupled to a power source; and
an authenticating circuit comprising a plurality of voltage measurement units, each voltage measurement unit to measure, at one or more frequencies over one or more periods of time, a local voltage at a respective functional unit of the plurality of functional units;
wherein the authenticating circuit is to produce, using the plurality of voltage measurement units, a power profile of the integrated circuit corresponding to a challenge function to be performed by one or more functional units of the plurality of functional units.

2. The integrated circuit of claim 1 , wherein each voltage measurement unit comprises a voltage-controlled oscillator (VCO) and a counter of voltage cycles produced by the VCO.

3. The integrated circuit of claim 1 , wherein the functional units are spatially distributed over a die.

4. The integrated circuit of claim 1 , wherein a first voltage measurement unit of the plurality of voltage measurement units is to measure a local voltage at a first functional unit of the plurality of functional units over a first period of time, and a second voltage measurement unit of the plurality of voltage measurement units is to measure a local voltage at a second functional unit of the plurality of functional units over a second period of time, the second period of time at least partially overlapping with the first period of time.

5. The integrated circuit of claim 1 , wherein a first voltage measurement unit of the plurality of voltage measurement units is to measure a local voltage at a first functional unit of the plurality of functional units over a first period of time, and a second voltage measurement unit of the plurality of voltage measurement units is to measure a local voltage at a second functional unit of the plurality of functional units over a second period of time, the second period of time not overlapping with the first period of time.

6. The integrated circuit of claim 1 , wherein the authenticating circuit is to further produce, using the plurality of voltage measurement units, an impedance profile of a power delivery system coupled to the power source, the impedance profile corresponding to a second challenge function to be performed by one or more functional units of the plurality of functional units.

7. The integrated circuit of claim 1 , further comprising a noise generation circuit comprising a plurality of noise generation units, each noise generation unit electrically coupled to a respective functional unit of the plurality of functional units.

8. The integrated circuit of claim 1 , wherein the challenge function comprises a plurality of memory read/write operations to be performed by the plurality of functional units utilizing pre-defined data patterns.

9. The integrated circuit of claim 1 , wherein the challenge function comprises a plurality of memory read/write operations to be performed by the plurality of functional units utilizing pre-defined address patterns.

10. An integrated circuit, comprising:
a plurality of functional units electrically coupled to a power source; and
an authenticating circuit comprising a plurality of voltage measurement units, each voltage measurement unit to measure, at one or more frequencies over one or more periods of time, a local voltage at a respective functional unit of the plurality of functional units;
wherein the authenticating circuit is to produce, using the plurality of voltage measurement units, an impedance profile of a power delivery system coupled to the power source, the impedance profile corresponding to a challenge function to be performed by one or more functional units of the plurality of functional units.

11. The integrated circuit of claim 10 , wherein each voltage measurement unit comprises a voltage-controlled oscillator (VCO) and a counter of voltage cycles produced by the VCO.

12. The integrated circuit of claim 10 , wherein the functional units are spatially distributed over a die.

13. The integrated circuit of claim 10 , wherein a first voltage measurement unit of the plurality of voltage measurement units is to measure a local voltage at a first functional unit of the plurality of functional units over a first period of time, and a second voltage measurement unit of the plurality of voltage measurement units is to measure a local voltage at a second functional unit of the plurality of functional units over a second period of time, the second period of time at least partially overlapping with the first period of time.

14. The integrated circuit of claim 10 , wherein a first voltage measurement unit of the plurality of voltage measurement units is to measure a local voltage at a first functional unit of the plurality of functional units over a first period of time, and a second voltage measurement unit of the plurality of voltage measurement units is to measure a local voltage at a second functional unit of the plurality of functional units over a second period of time, the second period of time not overlapping with the first period of time.

15. The integrated circuit of claim 10 , wherein the authenticating circuit is to further produce, using the plurality of voltage measurement units, a power profile of the integrated circuit corresponding to a second challenge function to be performed by one or more functional units of the plurality of functional units.

16. The integrated circuit of claim 10 , further comprising a noise generation circuit comprising a plurality of noise generation units, each noise generation unit electrically coupled to a respective functional unit of the plurality of functional units.

17. The integrated circuit of claim 10 , wherein the challenge function comprises a plurality of memory read/write operations to be performed by the plurality of functional units utilizing pre-defined data patterns.

18. The integrated circuit of claim 10 , wherein the challenge function comprises a plurality of memory read/write operations to be performed by the plurality of functional units utilizing pre-defined address patterns.

19. An integrated circuit, comprising:
a plurality of functional units electrically coupled to a power source; and
an authenticating circuit comprising a plurality of voltage measurement units, each voltage measurement unit to measure, at one or more frequencies over one or more periods of time, a local voltage at a respective functional unit of the plurality of functional units;
wherein the authenticating circuit is to:
produce, using the plurality of voltage measurement units, a quiescent power profile representing steady-state voltages when no input signals are applied to the functional units;
produce, using the plurality of voltage measurement units, a response power profile of the integrated circuit corresponding to a challenge function performed by one or more functional units of the plurality of functional units; and
produce, based on the quiescent power profile and response power profile, a differential power profile of the integrated circuit.

20. The integrated circuit of claim 19 , wherein the challenge function comprises a plurality of memory read/write operations to be performed by the plurality of functional units utilizing at least one of: a pre-defined data pattern or a pre-defined address pattern.

Assignees

• Cryptography Res Inc

Inventors

• Hampel Craig E
• Best Scott C

Classifications

• G01R31/31719 Primary

  Security aspects, e.g. preventing unauthorised access during test · CPC title

• G01R31/3008

  Quiescent current [IDDQ] test or leakage current test · CPC title

• G09C1/00

  Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title

• H04L9/3278

  using physically unclonable functions [PUF] · CPC title

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title