MOS transistor saturation region detector

Patent metadata

Field	Value
Publication number	US-9970979-B2
Application number	US-201514792142-A
Country	US
Kind code	B2
Filing date	Jul 6, 2015
Priority date	Jul 6, 2015
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

This application relates to a circuit for determining whether a first transistor device is in a predetermined operation mode. The circuit comprises comprising: a second transistor device, wherein control terminals of the first and second transistor devices are connected, and one of input and output terminals of the first transistor device is connected to the other one of input and output terminals of the second transistor device, a buffer amplifier connected between the one of input and output terminals of the first transistor device and the other one of input and output terminals of the second transistor device, and circuitry for determining whether the first transistor device is in the predetermined operation mode based on an indication of a current flowing through the second transistor device. The application further relates to a method of determining whether a first transistor device is in a predetermined operation mode.

First claim

What is claimed is:

1. A circuit for determining whether a first transistor device is in a predetermined operation mode, comprising:
a second transistor device, wherein gate terminals of the first and second transistor devices are connected, and a drain terminal of the first transistor device is connected to a source terminal of the second transistor device;
a buffer amplifier connected between the drain terminal of the first transistor device and the source terminal of the second transistor device, wherein an output of the buffer amplifier is directly connected to the source terminal of the second transistor device and an input of the buffer amplifier is supplied by the drain terminal of the first transistor device; and
a circuitry for determining whether the first transistor device is in the predetermined operation mode based on an indication of a current flowing through the second transistor device.

2. The circuit according to claim 1 , wherein the predetermined operation mode is a saturation mode.

3. The circuit according to claim 1 , wherein the buffer amplifier comprises an operational amplifier with its output port connected to its inverting input port.

4. The circuit according to claim 1 , further comprising a voltage source connected between the drain terminal of the first transistor device and the buffer amplifier.

5. The circuit according to claim 1 , wherein the circuitry for determining whether the first transistor device is in the predetermined operation mode is adapted to compare said current flowing through the second transistor device to a reference current.

6. The circuit according to claim 5 , wherein the circuitry for determining whether the first transistor device is in the predetermined operation mode comprises a current source for generating the reference current connected in series with the second transistor device and an inverter connected to an intermediate node between the second transistor device and the current source.

7. The circuit according to claim 5 , wherein the circuitry for determining whether the first transistor device is in the predetermined operation mode comprises a resistance element connected in series with the second transistor device and an inverter connected to an intermediate node between the second transistor device and the resistance element.

8. The method according to claim 1 , wherein said determining involves comparing said current flowing through the second transistor device to a reference current.

9. A method of determining whether a first transistor device is in a predetermined operation mode, the method comprising:
sensing a voltage at a drain terminal of the first transistor device;
supplying said sensed voltage to a buffer amplifier as an input of the buffer amplifier;
supplying an output of the buffer amplifier to a source terminal of a second transistor device, wherein the output of the buffer amplifier is directly connected to the source terminal of the second transistor device, and wherein gate terminals of the first and second transistor devices are connected; and
determining whether the first transistor device is in the predetermined operation mode based on an indication of a current flowing through the second transistor device.

10. The method according to claim 9 , wherein the predetermined operation mode is a saturation mode.

11. The method according to claim 9 , wherein the buffer amplifier comprises an operational amplifier with its output port connected to its inverting input port.

12. The method according to claim 9 , further comprising adding an offset voltage to said sensed voltage.

Assignees

• Dialog Semiconductor Uk Ltd

Inventors

• Gerna Danilo
• Pardi Enrico
• Kesterson John

Classifications

• G01R31/2621 Primary

  for testing field effect transistors, i.e. FET's · CPC title

• G01R1/30

  Structural combination of electric measuring instruments with basic electronic circuits, e.g. with amplifier · CPC title