Three-dimensional passive components

Patent metadata

Field	Value
Publication number	US-9969001-B2
Application number	US-201514964451-A
Country	US
Kind code	B2
Filing date	Dec 9, 2015
Priority date	Dec 10, 2014
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

Three-dimensional inductors may comprise a passivation layer disposed on a substrate, a three-dimensional pillar comprising a ferromagnetic material disposed on the substrate or the passivation layer, and a conductive trace wound at least partially around the pillar. Three-dimensional capacitors may comprise a passivation layer disposed on a substrate, at least two support pillars comprising a polymeric material disposed on the passivation layer or the substrate, at least two electrodes disposed between the support pillars, a dielectric disposed between the electrodes, and a metal trace. Methods of manufacturing the three-dimensional passives, such as inductors and capacitors, may comprise direct writing the components and curing them for on-chip applications.

First claim

What is claimed is:

1. A device comprising:
a substrate;
a pillar disposed on at least a portion of the substrate layer, the pillar including at least one of a ferromagnetic material or a polymer, the pillar defining a three-dimensional structure projecting out from the substrate between approximately 1 μm and approximately 1 mm; and
a conductive trace wound at least partially around the pillar.

2. The device of claim 1 , wherein:
the ferromagnetic material comprises iron, barium titanate, germanium telluride, polyvinylidene fluoride, or a combination thereof; and
the polymer comprises acrylate urethane.

3. The device of claim 1 , wherein the conductive trace comprises sintered silver, cupric oxide, copper, platinum, gold, aluminum, a conducting polymer, or a combination thereof.

4. The device of claim 1 , further comprising a passivation layer disposed between the substrate and the pillar.

5. The device of claim 4 , wherein the pillar abuts a surface of the passivation layer.

6. A device comprising:
a silicon chip;
at least two support pillars disposed on at least a portion of the silicon chip, the at least two support pillars comprising a polymeric material;
at least two electrodes disposed between the at least two support pillars;
a dielectric disposed at least partially between the at least two electrodes and in contact with the at least two electrodes; and
a conductive trace in contact with the at least two support pillars, the at least two electrodes, and the dielectric.

7. The device of claim 6 , wherein the dielectric comprises barium titanate, a polymer, a composite of barium titanate and the polymer, or air.

8. The device of claim 6 , further comprising passivation layer disposed between the two support pillars and the substrate.

9. The device of claim 8 , wherein the three-dimensional capacitor projects out from the substrate between approximately 1 μm and approximately 1 mm.

10. The device of claim 6 , wherein the at least two support pillars comprise a conductive material and serve as the at least two electrodes.

Assignees

• Univ Washington State

Inventors

• Panat Rahul P
• Heo Deuk H

Classifications

• B22F12/37

  Rotatable · CPC title

• B22F10/10 Primary

  Formation of a green body · CPC title

• B22F10/20

  Direct sintering or melting · CPC title

• H05K1/0313

  Organic insulating material · CPC title

• H05K3/4644

  by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602) · CPC title