Frequency modulation receiver and frequency modulation receiving method

Patent metadata

Field	Value
Publication number	US-9967086-B2
Application number	US-201715397861-A
Country	US
Kind code	B2
Filing date	Jan 4, 2017
Priority date	Jul 1, 2016
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

A frequency modulation receiver includes a frequency modulation demodulation circuit that generates a first signal, and a phase locked loop (PLL) circuit coupled to the frequency modulation demodulation circuit to receive the first signal. The PLL circuit includes: a voltage-controlled oscillator (VCO), generating an oscillation output signal according to a filtered output signal; a phase detector, coupled to the VCO, generating a phase signal according to the oscillation output signal and the first signal; and a proportional-integral-derivative (PID) filter, coupled to the VCO and the phase detector, receiving the phase signal and generating the filtered output signal to the VCO.

First claim

What is claimed is:

1. A frequency modulation receiver, comprising:
a frequency modulation demodulation circuit, generating a first signal; and
a first phase locked loop (PLL) circuit, coupled to the frequency modulation demodulation circuit to receive the first signal, the PLL circuit comprising:
a voltage-controlled oscillator (VCO), generating an oscillation output signal according to a filtered output signal;
a phase detector, coupled to the VCO, comprising a phase extractor for generating a phase signal according to the oscillation output signal and the first signal; and
a proportional-integral-derivative (PID) filter, coupled to the VCO and the phase detector, receiving the phase signal and generating the filtered output signal to the VCO, the PID filter comprising:
a proportion circuit, multiplying the phase signal by a proportion coefficient to generate a proportion result;
an integration circuit, performing an integration calculation on the phase signal, and multiplying the integration calculation result by an integration coefficient to generate an integration result;
a differentiation circuit, performing a differentiation calculation on the phase signal, and multiplying the differentiation calculation result by a differentiation coefficient to generate a differentiation result; and

a summation circuit, generating the filtered output signal according to the proportion result, the integration result and the differentiation result,
wherein the phase detector comprises:
a mixer, mixing the first signal with the oscillation output signal to generate a mixed result; and
a low-pass filter, performing a low-pass filter operation on the mixed result to generate a low-frequency signal,
wherein the phase extractor extracts a phase of the low-frequency signal to generate the phase signal.

2. The frequency modulation receiver according to claim 1 , wherein the integration circuit comprises:
a first buffer, generating a first buffered output signal; and
an adder, adding the first buffered output signal with the phase signal to generate an addition result;
wherein, the first buffer generates the first buffered output signal according to the addition result, and the integration circuit multiplies the addition result by the integration coefficient to generate the integration result.

3. The frequency modulation receiver according to claim 1 , wherein the differentiation circuit comprises:
a second buffer, generating a second buffered output signal according to the phase signal; and
a subtractor, subtracting the second buffered output signal from the phase signal to generate a subtraction result;
wherein, the differentiation circuit multiplies the subtraction result by the differentiation coefficient to generate the differentiation result.

4. The frequency modulation receiver according to claim 1 , further comprising:
a coefficient adjusting circuit, adjusting the proportion coefficient, the integration coefficient and the differentiation coefficient after the PLL operates for a predetermined period of time.

5. A frequency modulation receiving method, applied to a frequency modulation receiver to track a frequency or a phase of a single-tone signal of a first signal, the frequency modulation receiver comprising a frequency modulation demodulation circuit and a phase locked loop (PLL) circuit, the PLL circuit comprising a voltage-controlled oscillator (VCO) and a phase detector, the frequency modulation receiving method comprising:
generating the first signal by the frequency modulation demodulation circuit;
generating a phase signal according to the first signal and an oscillation output signal that the VCO generates by a phase extractor of the phase detector;
multiplying the phase signal by a proportion coefficient to generate a proportion result;
performing an integration calculation on the phase signal, and multiplying the integration calculation result by an integration coefficient to generate an integration result;
performing a differentiation calculation on the phase signal, and multiplying the differentiation calculation result by a differentiation coefficient to generate a differentiation result;
generating the filtered output signal according to the proportion result, the integration result and the differentiation result; and
generating the oscillation output signal according to the filtered output signal by the VCO;
wherein, the PLL circuit approximates the frequency or the phase of the single-tone signal according to the oscillation output signal and the step of generating the phase signal according to the first signal and the oscillation output signal comprises:
mixing the first signal with the oscillation output signal to generate a mixed result;
performing a low-pass filter operation on the mixed result to generate a low-frequency signal; and
extracting a phase of the low-frequency signal to generate the phase signal.

6. The frequency modulation receiving method according to claim 5 , further comprising:
adjusting the proportion coefficient, the integration coefficient and the differentiation coefficient after a predetermined period of time.

Assignees

• Mstar Semiconductor Inc

Inventors

• Su Yu-Che
• Lee Kuan-Chou
• Tung Tai-Lai

Classifications

• H04L2027/0067

  Phase error detectors · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H04L27/14

  Demodulator circuits; Receiver circuits · CPC title

• H04L27/227 Primary

  using coherent demodulation · CPC title

• H04L7/0331 Primary

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title