Semiconductor integrated circuits

Patent metadata

Field	Value
Publication number	US-9966936-B2
Application number	US-201615172182-A
Country	US
Kind code	B2
Filing date	Jun 3, 2016
Priority date	Sep 10, 2015
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

A semiconductor integrated circuit includes a scan enable (SE) inverter and a clock (CK) inverter on a substrate, a first multiplex part, and a second multiplex part. The SE inverter and the CK inverter are aligned in a first direction. The first multiplex part includes a first wiring and a first transistor, the first wiring is connected to a power supply voltage part of the SE inverter, and the first wiring and the first transistor share a source region contacting the first wiring. The second multiplex part includes a second wiring and a second transistor, the second wiring is connected to a power supply voltage part of the CK inverter, and the second wiring and the second transistor share a source region contacting the second wiring. The SE inverter and the CK inverter are aligned in a first direction to each other.

First claim

What is claimed is:

1. A semiconductor integrated circuit comprising:
a scan enable (SE) inverter and a clock (CK) inverter on a substrate, the SE inverter and the CK inverter being aligned in a first direction to each other, wherein a first gate of the SE inverter and a second gate of the CK inverter are disposed on one imaginary line extending in the first direction;
a first multiplex part including a first wiring and a first transistor, the first wiring being connected to a power supply voltage part of the SE inverter, and the first wiring and the first transistor sharing a source region contacting the first wiring; and
a second multiplex part including a second wiring and a second transistor, the second wiring being connected to a power supply voltage part of the CK inverter, and the second wiring and the second transistor sharing a source region contacting the second wiring, wherein:
the power supply voltage parts of the SE inverter and the CK inverter include a first VDD line and a second VDD line, respectively, each of the first and second VDD lines extending in a second direction substantially perpendicular to the first direction, and
the first wiring is connected with the first VDD line, and the second wiring is connected with the second VDD line.

2. The semiconductor integrated circuit of claim 1 , wherein the CK inverter is disposed under the SE inverter in the first direction.

3. The semiconductor integrated circuit of claim 1 , wherein the CK inverter is disposed over the SE inverter in the first direction.

4. The semiconductor integrated circuit of claim 1 , further comprising a ground line extending in the second direction, wherein the SE inverter and the CK inverter are connected with the ground line.

5. The semiconductor integrated circuit of claim 1 , the power supply voltage parts of the SE inverter and the CK inverter include a VDD line extending in a second direction, wherein the first and second wirings are connected with the VDD line.

6. The semiconductor integrated circuit of claim 5 , further comprising:
a first ground line and a second ground line each extending in the second direction, wherein
the SE inverter is connected with the first ground line, and the CK inverter is connected with the second ground line.

7. The semiconductor integrated circuit of claim 1 , wherein the CK inverter and the SE inverter are formed in areas of the substrate, the areas having substantially the same size.

8. The semiconductor integrated circuit of claim 1 , wherein a first gate of the SE inverter and a second gate of the CK inverter are aligned in the first direction.

9. The semiconductor integrated circuit of claim 1 , further comprising:
a first master part, a first slave part and a first output part disposed adjacent to the first multiplex part in this order in a second direction; and
a second master part, a second slave part and a second output part disposed adjacent to the second multiplex part in this order in the second direction.

10. The semiconductor integrated circuit of claim 9 , wherein the first master part, the first slave part and the first output part are aligned in the first direction to the second master part, the second slave part and the second output part, respectively.

11. A semiconductor integrated circuit comprising:
a substrate including a first region for processing a first bit and a second region for processing a second bit, the second region being under the first region in a first direction;
a scan enable (SE) inverter and a clock (CK) inverter on the substrate, the SE inverter and the CK inverter being aligned to each other in the first direction;
a first multiplex part adjacent to the SE inverter in a second direction substantially perpendicular to the first direction, the first multiplex part including a first wiring and a first transistor, the first wiring being connected to a power supply voltage of the SE inverter, and the first wiring and the first transistor sharing an impurity region contacting the first wiring; and
a second multiplex part including a second wiring and a second transistor, the second wiring being connected to a power supply voltage of the CK inverter, and the second wiring and the second transistor sharing an impurity region contacting the second wiring.

12. The semiconductor integrated circuit of claim 11 , further comprising:
a first VDD line, a second VDD line and a ground line each extending in the second direction, wherein
the first VDD line is formed at an upper portion of the first region, the second VDD line is formed at a lower portion of the second region, and the ground line is formed between the first and second regions.

13. The semiconductor integrated circuit of claim 12 , wherein:
the first wiring is connected to one of the first VDD line and the second VDD line adjacent to the first wiring, and
the second wiring is connected to another one of the first VDD line and the second VDD line.

14. The semiconductor integrated circuit of claim 11 , wherein:
the SE inverter includes a first gate extending in the first direction on first and second active regions, the first and second active regions being substantially parallel with each other, and
the CK inverter includes a second gate extending in the first direction on third and fourth active regions, the third and fourth active regions being substantially parallel with each other.

15. A flip-flop comprising:
a first inverter comprising a first PMOS transistor and a first NMOS transistor;
a second inverter comprising a second PMOS transistor and a second NMOS transistor;
a first tri-state buffer comprising third and fourth PMOS transistors and third and fourth NMOS transistors;
a first active region in which the first, third, and fourth PMOS transistors are formed; and
a second active region in which the first, third, and fourth NMOS transistors are formed, wherein:
a first portion of the first active region operates as a source for each of the first and third PMOS transistors,
a first portion of the second active region operates as a source for each of the first and fourth NMOS transistors,
a second portion of the first active region operates as a drain for the third PMOS transistor and a source for the fourth PMOS transistor,
a second portion of the second active region operates as a drain for the fourth NMOS transistor and a source for the third NMOS transistor,
a first gate extends longitudinally in a first direction so as to overlap the first and second active regions and constitutes a gate for each of the first PMOS transistor and the first NMOS transistor,
a second gate: (1) extends longitudinally in the first direction so as to overlap a third active region in which the second PMOS transistor is formed and a fourth active region in which the second NMOS transistor is formed and (2) constitutes a gate for each of the second PMOS transistor and the second NMOS transistor, and
the first and second gates are aligned along the first direction.

16. The flip-flop of claim 15 , wherein a third gate overlaps the first and second active regions and constitutes a gate for each of the third PMOS transistor and the fourth NMOS transistor.

17. The flip-flop of claim 16 , wherein the first PMOS transistor and the first NMOS transistor are aligned and the third PMOS transistor and the fourth NMOS transistor are aligned in parallel with the alignment of the first PMOS transistor and the first NMOS transistor.

18. The flip-flop of claim 17 , wherein the first and second gates are separated by one gate pitch.

Assignees

• Kim Ji Kyum
• Lee Dae Seong
• Kim Min Su
• Samsung Electronics Co Ltd

Inventors

• Kim Ji-Kyum
• Lee Dae-Seong
• Kim Min-Su

Classifications

• H03K3/353 Primary

  by the use, as active elements, of field-effect transistors with internal or external positive feedback (H03K3/023, H03K3/027 take precedence) · CPC title

• H03K3/01

  Details · CPC title

• G01R31/318541 Primary

  Scan latches or cell details · CPC title

• H03K3/35625 Primary

  using complementary field-effect transistors · CPC title