Metal-insulator-metal (MIM) capacitor with an electrode scheme for improved manufacturability and reliability

Patent metadata

Field	Value
Publication number	US-9966427-B2
Application number	US-201615154027-A
Country	US
Kind code	B2
Filing date	May 13, 2016
Priority date	May 13, 2016
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

A method for manufacturing a metal-insulator-metal (MIM) capacitor with a top electrode that is free of sidewall damage is provided. A bottom electrode layer is formed with a first material. An inter-electrode dielectric layer is formed over the bottom electrode layer. A top electrode layer is formed over the inter-electrode dielectric layer and without the first material. A first etch is performed into the top electrode layer and the inter-electrode dielectric layer to form a top electrode. A second etch into the bottom electrode layer to form a bottom electrode. The present application is also directed towards a MIM capacitor resulting from performing the method.

First claim

What is claimed is:

1. A method of forming a capacitor, the method comprising:
forming a bottom electrode layer with a first material;
forming an inter-electrode dielectric layer over the bottom electrode layer;
forming a top electrode layer over the inter-electrode dielectric layer, wherein the top electrode layer is formed without disposing the first material;
performing a first etch into the top electrode layer and the inter-electrode dielectric layer to form a top electrode;
forming a capping layer covering the bottom electrode layer and the top electrode, wherein the capping layer extends along and contacts sidewalls of the top electrode and the inter-electrode dielectric layer, and wherein the capping layer extends laterally along and contacts a top surface of the bottom electrode layer;
forming a photoresist layer on the capping layer; and
performing a second etch into the capping layer and the bottom electrode layer with the photoresist layer in place, wherein the second etch forms a bottom electrode.

2. The method according to claim 1 , further comprising:
forming the top electrode layer with only a second material different than the first material.

3. A method of forming a capacitor, the method comprising:
forming a bottom electrode layer with a first material, wherein the forming of the bottom electrode layer comprises:
forming a first diffusion barrier layer of a second material and over a lower portion of an interconnect structure;
forming a metal layer of the first material and over the first diffusion barrier layer; and
forming a second diffusion barrier layer of the second material and over the metal layer;

forming an inter-electrode dielectric layer over the bottom electrode layer;
forming a top electrode layer over the inter-electrode dielectric layer, wherein the top electrode layer is formed without disposing the first material;
performing a first etch into the top electrode layer and the inter-electrode dielectric layer to form a top electrode;
forming a capping layer covering the bottom electrode layer and the top electrode, wherein the capping layer extends along and contacts sidewalls of the top electrode and the inter-electrode dielectric layer, and wherein the capping layer extends laterally along and contacts a top surface of the bottom electrode layer;
forming a photoresist layer on the capping layer; and
performing a second etch into the capping layer and the bottom electrode layer with the photoresist layer in place, wherein the second etch forms a bottom electrode.

4. The method according to claim 1 , further comprising:
forming a first anti-reflective layer over and contacting a top surface of the top electrode layer, wherein the first anti-reflective layer has a same width as the top electrode, and wherein the capping layer is further formed over the first anti-reflective layer and lining sidewalls the first anti-reflective layer; and
performing the first etch into the first anti-reflective layer.

5. The method according to claim 4 , further comprising:
forming a second anti-reflective layer over and lining the capping layer, wherein the second anti-reflective layer, the bottom electrode, and the capping layer have the same widths; and
performing the second etch into the second anti-reflective layer.

6. The method according to claim 4 , further comprising:
performing plasma treatment of the top electrode to remove native oxide on the top electrode, wherein the performing of the plasma treatment comprises generating plasma from nitrous oxide gas; and
immediately following the plasma treatment, forming the capping layer.

7. A method of forming a capacitor, the method comprising:
forming a bottom electrode layer on a substrate, wherein the bottom electrode layer comprises copper;
forming an inter-electrode dielectric layer on the bottom electrode layer;
forming a top electrode layer on the inter-electrode dielectric layer, wherein the top electrode layer is devoid of copper;
forming a first photoresist layer on the top electrode layer;
performing a first etch into the top electrode layer and the inter-electrode dielectric layer with the first photoresist layer in place to form a top electrode and an inter-electrode dielectric structure spacing the top electrode over the bottom electrode layer;
performing a stripping process to strip the first photoresist layer without damaging a sidewall of the top electrode; and
performing a second etch into the bottom electrode layer to form a bottom electrode.

8. The method according to claim 7 , further comprising:
forming a second photoresist layer on the top electrode and the bottom electrode layer;
performing the second etch into the bottom electrode layer with the second photoresist layer in place to form the bottom electrode; and
performing the stripping process to strip the second photoresist layer, wherein stripping the second photoresist layer damages a copper sidewall of the bottom electrode.

9. The method according to claim 7 , wherein forming the bottom electrode layer comprises:
forming a first diffusion barrier layer on the substrate;
forming a copper-based layer on the first diffusion barrier layer; and
forming a second diffusion barrier layer on the copper-based layer, wherein the first and second diffusion barrier layers are the same material as the top electrode layer, and wherein the first and second diffusion barrier layers and the copper-based layer define the bottom electrode layer.

10. The method according to claim 9 , wherein the copper-based layer contacts the first diffusion barrier layer, wherein the second diffusion barrier layer contacts the copper-based layer, wherein the inter-electrode dielectric layer contacts the second diffusion barrier layer, and wherein the top electrode layer contacts the inter-electrode dielectric layer.

11. The method according to claim 10 , further comprising:
forming an interlayer dielectric (ILD) layer covering the top and bottom electrodes and the inter-electrode dielectric structure; and
forming a via extending through the ILD layer and contacting a top surface of the top electrode.

12. The method according to claim 1 , further comprising:
forming an interlayer dielectric (ILD) layer covering the top and bottom electrodes and the inter-electrode dielectric layer; and
forming a pair of vias extending through the ILD layer respectively to the top and bottom electrodes, wherein a first via of the pair is formed overlying and contacting the top electrode, wherein a second via of the pair is formed overlying and contacting the bottom electrode, wherein the first and second vias are formed laterally contacting sidewalls of the capping layer, and wherein the first and second vias have the same widths.

13. The method according to claim 8 , further comprising:
forming a first anti-reflective layer on the top electrode layer, wherein the first photoresist layer is formed on the first anti-reflective layer, and wherein the first etch is further performed into the first anti-reflective layer with the first photoresist layer in place;
forming a capping layer covering and contacting the bottom electrode layer and the first anti-reflective layer, wherein the capping layer laterally contacts sidewalls of the first anti-reflective layer, the top electrode, and the inter-electrode dielectric structure;
forming a second anti-reflective layer covering and conformally lining the capping layer, wherein the second anti-reflective layer contacts the capping layer, and wherein the first and second anti-reflective layers are the same material;
wherein the second photoresist layer is furthe

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Cheng Shyh-Wei
• Chen Hung-Lin
• Weng Jui-Chun
• Lin Shiuan-Jeng
• Lin Tian Sheng
• Wu Yu-Jui
• Pan Albion
• Sun Bob

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10W20/496 Primary

  Capacitor integral with wiring layers · CPC title

• H01L23/5223

  Electricity · mapped topic

• H01L28/75 Primary

  Electricity · mapped topic