Complementary thin film transistor and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9966415-B2
Application number	US-201615034355-A
Country	US
Kind code	B2
Filing date	Apr 8, 2016
Priority date	Feb 29, 2016
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

A complementary thin film transistor and manufacturing method thereof are provided. The complementary thin film transistor has a substrate, an n-type semiconductor layer, a p-type semiconductor layer, a first passivation layer, a first electrode metal layer, and a second electrode metal layer. The n-type semiconductor layer is disposed above the substrate, and comprises a metal oxide material. The p-type semiconductor layer is disposed above the substrate, and comprises an organic semiconductor material. The first passivation layer is disposed between the n-type semiconductor layer and the p-type semiconductor layer, and formed with at least one contacting hole. The first electrode metal layer and the second electrode metal layer are electrically connected with each other through the contacting hole.

First claim

What is claimed is:

1. A complementary thin film transistor, comprising:
a substrate;
an n-type semiconductor layer disposed above the substrate, wherein the n-type semiconductor layer comprises a metal oxide material, and the metal oxide material of the n-type semiconductor layer is selected from an indium gallium zinc oxide, an indium zinc oxide, or a zinc tin oxide;
a p-type semiconductor layer disposed above the substrate, wherein the p-type semiconductor layer comprises an organic semiconductor material, and the organic semiconductor material of the p-type semiconductor layer is selected from pentacene, triphenylamine, fullerene, phthalocyanine, perylene derivative, or cyanine;
a first passivation layer disposed between the n-type semiconductor layer and the p-type semiconductor layer, and formed with at least one contacting hole;
a first electrode metal layer formed on the n-type semiconductor layer; and
a second electrode metal layer formed on the first passivation layer, wherein the first electrode metal layer and the second electrode metal layer are electrically connected with each other through the contacting hole.

2. The complementary thin film transistor according to claim 1 , wherein the complementary thin film transistor further includes a first gate layer and an insulation layer, the first gate layer is formed on the substrate, and the insulation layer is formed on the first gate layer and the substrate, wherein the n-type semiconductor layer is formed on the insulation layer.

3. The complementary thin film transistor according to claim 2 , wherein the first electrode metal layer is formed on the insulation layer and the n-type semiconductor layer.

4. The complementary thin film transistor according to claim 2 , wherein the complementary thin film transistor further includes a second passivation layer and a second gate layer, the second passivation layer is formed on the second electrode metal layer, the first passivation layer and the p-type semiconductor layer, and the second gate layer is formed on the second passivation layer.

5. The complementary thin film transistor according to claim 2 , wherein the complementary thin film transistor further includes an etched barrier layer formed on the n-type semiconductor layer and the insulation layer.

6. The complementary thin film transistor according to claim 5 , wherein the first electrode metal layer of the complementary thin film transistor is formed on the insulation layer and the n-type semiconductor layer.

7. The complementary thin film transistor according to claim 5 , wherein the complementary thin film transistor further includes a second passivation layer and a second gate layer, the second passivation layer is formed on the second electrode metal layer, the first passivation layer and the p-type semiconductor layer, and the second gate layer is formed on the second passivation layer.

8. A complementary thin film transistor, comprising:
a substrate;
an n-type semiconductor layer disposed above the substrate, wherein the n-type semiconductor layer comprises a metal oxide material;
a p-type semiconductor layer disposed above the substrate, wherein the p-type semiconductor layer comprises an organic semiconductor material;
a first passivation layer disposed between the n-type semiconductor layer and the p-type semiconductor layer, and formed with at least one contacting hole;
a first electrode metal layer formed on the n-type semiconductor layer; and
a second electrode metal layer formed on the first passivation layer, wherein the first electrode metal layer and the second electrode metal layer are electrically connected with each other through the contacting hole.

9. The complementary thin film transistor according to claim 8 , wherein the complementary thin film transistor further includes a first gate layer and an insulation layer, the first gate layer is formed on the substrate, and the insulation layer is formed on the first gate layer and the substrate, wherein the n-type semiconductor layer is formed on the insulation layer.

10. The complementary thin film transistor according to claim 9 , wherein the first electrode metal layer is formed on the insulation layer and the n-type semiconductor layer.

11. The complementary thin film transistor according to claim 9 , wherein the complementary thin film transistor further includes a second passivation layer and a second gate layer, the second passivation layer is formed on the second electrode metal layer, the first passivation layer and the p-type semiconductor layer, and the second gate layer is formed on the second passivation layer.

12. The complementary thin film transistor according to claim 9 , wherein the complementary thin film transistor further includes an etched barrier layer formed on the n-type semiconductor layer and the insulation layer.

13. The complementary thin film transistor according to claim 12 , wherein the first electrode metal layer of the complementary thin film transistor is formed on the insulation layer and the n-type semiconductor layer.

14. The complementary thin film transistor according to claim 12 , wherein the complementary thin film transistor further includes a second passivation layer and a second gate layer, the second passivation layer is formed on the second electrode metal layer, the first passivation layer and the p-type semiconductor layer, and the second gate layer is formed on the second passivation layer.

15. The complementary thin film transistor according to claim 8 , wherein the metal oxide material of the n-type semiconductor layer is selected from an indium gallium zinc oxide, an indium zinc oxide, or a zinc tin oxide.

16. The complementary thin film transistor according to claim 8 , wherein the organic semiconductor material of the p-type semiconductor layer is selected from pentacene, triphenylamine, fullerene, phthalocyanine, perylene derivative, or cyanine.

17. A manufacturing method of a complementary thin film transistor, comprising steps of:
a first gate layer formation step for disposing a first gate layer on a substrate;
an insulation layer formation step for forming an insulation layer on the first gate layer and the substrate;
an n-type semiconductor layer formation step for forming an n-type semiconductor layer on the insulation layer, wherein the n-type semiconductor layer comprises a metal oxide material;
a first electrode metal layer formation step for forming a first electrode metal layer on the n-type transistor region and the insulation layer;
a first passivation layer formation step for a first passivation layer on the n-type semiconductor layer, the first passivation layer and the insulation layer, and forming at least one contacting hole;
a second electrode metal layer formation step for forming a second electrode metal layer on the first passivation layer, wherein the first electrode metal layer and the second electrode metal layer are electrically connected with each other through the contacting hole; and
a p-type semiconductor layer formation step forming a p-type semiconductor layer on the first passivation layer and the second electrode metal layer, wherein the p-type semiconductor layer comprises an organic semiconductor material.

18. The manufacturing method according to claim 17 , wherein after the n-type semiconductor layer formation step, the manufacturing method further comprises an etched barrier layer formation step for forming an etched barrier layer on the n-type semiconductor layer and the insulation layer.

19. The man

Assignees

• Shenzhen China Star Optoelect

Inventors

• Zeng Mian
• Hsiao Hsiangchih
• Zhang Shengdong

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H01L51/0541

  Electricity · mapped topic

• H01L27/283 Primary

  Electricity · mapped topic

• H01L51/0021

  Electricity · mapped topic

• H01L51/0558

  Electricity · mapped topic