Semiconductor structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9966383-B2
Application number	US-201514950424-A
Country	US
Kind code	B2
Filing date	Nov 24, 2015
Priority date	Oct 15, 2015
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, a non-volatile memory cell, and a gate stack. The non-volatile memory cell is formed in the semiconductor substrate, and a top surface of the non-volatile memory cell is coplanar with or below a top surface of the semiconductor substrate. The gate stack is formed on the semiconductor substrate.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a semiconductor substrate;
a non-volatile memory cell formed in the semiconductor substrate, wherein a top surface of the non-volatile memory cell is coplanar with or below a top surface of the semiconductor substrate;
an oxide layer formed on the semiconductor substrate;
an interlayer dielectric formed on the semiconductor substrate;
a logic gate formed in the interlayer dielectric and on the oxide layer, wherein a bottom surface of the logic gate is above the top surface of the non-volatile memory cell;
a contact plug formed in the interlayer dielectric, wherein the top surface of the non-volatile memory cell is under a bottom surface of the interlayer dielectric and the contact plug, and the contact plug is electrically connected to the non-volatile memory cell; and
a bit line formed in the semiconductor substrate, wherein a top surface of the bit line is coplanar with the top surface of the non-volatile memory cell;
wherein the non-volatile memory cell comprises:
a floating gate dielectric;
a floating gate formed on the floating gate dielectric;
a control gate formed above the floating gate;
a word line formed on a first side of the floating gate and a first side of the control gate; and
an erase gate formed on a second side of the floating gate and a second side of the control gate, the second sides being opposite to the first sides of the floating gate and the control gate.

2. The semiconductor structure according to claim 1 , further comprising:
a source line formed below the erase gate;
wherein the bit line is located on a lateral side of the word line opposite to the floating gate and the control gate.

3. The semiconductor structure according to claim 1 , wherein the non-volatile memory cell further comprises:
a memory structure formed on sidewalls of the control gate.

4. The semiconductor structure according to claim 1 , wherein the non-volatile memory cell further comprises:
a silicide layer formed on top surfaces of the word line, the control gate, and the erase gate.

5. The semiconductor structure according to claim 1 , further comprising:
an isolation structure formed in the semiconductor substrate and located between the non-volatile memory cell and the logic gate.

6. The semiconductor structure according to claim 1 , wherein the non-volatile memory cell has a first depth extending toward inside of the semiconductor substrate, the logic gate has a first height, and the first depth is larger than the first height.

7. The semiconductor structure according to claim 1 , wherein the logic gate comprises:
a high-voltage gate.

Assignees

• United Microelectronics Corp

Inventors

• Yi Liang
• Chen Ko-Chi
• Wang Shen-De

Classifications

• H01L29/4236

  Electricity · mapped topic

• H01L27/11578 Primary

  Electricity · mapped topic

• H10D64/513 Primary

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H10D30/6894

  having one gate at least partly in a trench · CPC title