Semiconductor device

Patent metadata

Field	Value
Publication number	US-9966375-B2
Application number	US-201615049648-A
Country	US
Kind code	B2
Filing date	Feb 22, 2016
Priority date	Apr 24, 2015
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

A semiconductor device includes a compound semiconductor layer, where the compound semiconductor layer includes separate fin patterns in separate regions. The separate fin patterns may include different materials. The separate fin patterns may include different dimensions, including one or more of width and height of one or more portions of the fin patterns. The separate fin patterns may include an upper pattern and a lower pattern. The upper pattern and the lower pattern may include different materials. The upper pattern and the lower pattern may include different dimensions. Separate regions may include separate ones of an NMOS or a PMOS. The semiconductor device may include gate electrodes on the compound semiconductor layer. Separate gate electrodes may intersect the separate fin patterns.

First claim

What is claimed is:

1. A semiconductor device comprising:
a compound semiconductor layer, the compound semiconductor layer including a first region and a second region;
a first fin pattern protruding from the compound semiconductor layer in the first region, the first fin pattern including a first lower pattern and a first upper pattern, the first upper pattern on the first lower pattern; and
a second fin pattern protruding from the compound semiconductor layer in the second region, the second fin pattern includes a second lower pattern and a second upper pattern, the second upper pattern on the second lower pattern,
wherein the first upper pattern includes a first material and the second upper pattern includes a second material, the first material and the second material each being different from a material composition of the compound semiconductor layer, the second material being different from the first material,
wherein the first fin pattern is associated with a first width and the second fin pattern is associated with a second width, the second width being narrower than the first width,
wherein the first region is a region in which an NMOS is formed and the second region is a region in which a PMOS is formed,
wherein a width of the second upper pattern is different from a width of the second lower pattern at a boundary between the second upper pattern and the second lower pattern, such that a step difference is formed between a sidewall of a trench that defines the second upper pattern and a sidewall of the trench that defines the second lower pattern.

2. The semiconductor device of claim 1 , wherein
the first material is associated with a first lattice constant,
the second material is associated with a second lattice constant, and
the first lattice constant is different from than the second lattice constant.

3. The semiconductor device of claim 2 , wherein
the first lattice constant is different from than a lattice constant of a material included in the first lower pattern, and
the second lattice constant is different from a lattice constant of a material included in the second lower pattern.

4. The semiconductor device of claim 1 , wherein a height of the first upper pattern is different from a height of the second upper pattern.

5. The semiconductor device of claim 1 , wherein a width of the first upper pattern is different from a width of the second upper pattern.

6. The semiconductor device of claim 1 , wherein a height of the first fin pattern is different from a height of the second fin pattern.

7. A semiconductor device comprising:
a compound semiconductor layer, the compound semiconductor layer including a first region and a second region;
a first fin pattern, the first fin pattern including a first lower pattern and a first upper pattern, the first lower pattern and the first upper being sequentially stacked on the compound semiconductor layer in the first region such that the first upper pattern is directly on the first lower pattern, the first fin pattern being defined by a first trench having a first depth; and
a second fin pattern, the second fin pattern including a second lower pattern and a second upper pattern, the second lower pattern and the second upper pattern being sequentially stacked on the compound semiconductor layer in the second region such that the second upper pattern is directly on the second lower pattern, the second fin pattern being defined by a second trench having a second depth, the second depth being different from the first depth;
wherein the first lower pattern and second lower pattern are each integral with the compound semiconductor layer and have a common material composition with a material composition of the compound semiconductor layer;
wherein the first upper pattern includes a first material and the second upper pattern including a second material, the first upper pattern and the second upper pattern each being a separate and integral pattern, the first material and the second material each being different from the material composition of the compound semiconductor layer, the second material being different from the first material, the first upper pattern and the second upper pattern each configured to be a channel region of a transistor,
wherein a width of the second upper pattern is narrower than a width of the second lower pattern at a boundary between the second upper pattern and the second lower pattern, such that a step difference is formed between a sidewall of a trench that defines the second upper pattern and a sidewall of the trench that defines the second lower pattern.

8. The semiconductor device of claim 7 , wherein
a lattice constant of the first material included is different from a lattice constant of the second material.

9. The semiconductor device of claim 7 , wherein the first material includes silicon and the second material includes silicon germanium.

10. The semiconductor device of claim 7 , wherein a height of the first lower pattern is different from a height of the second lower pattern.

11. The semiconductor device of claim 7 , wherein a width of the first upper pattern is different from a width of the second upper pattern.

12. The semiconductor device of claim 7 , wherein a width of the first upper pattern is narrower than a width of the first lower pattern at a boundary between the first upper pattern and the first lower pattern, such that a step difference is formed between a sidewall of another trench that defines the first upper pattern and a sidewall of the other trench that defines the first lower pattern.

13. A semiconductor device comprising:
a compound semiconductor layer, the compound semiconductor layer including a first region and a second region, the compound semiconductor layer including silicon germanium;
a first fin pattern, the first fin pattern including a first lower pattern and a first upper pattern, the first lower pattern and the first upper pattern being sequentially stacked on the compound semiconductor layer in the first region such that the first upper pattern is directly on the first lower pattern, the first lower pattern being a silicon germanium pattern, the first upper pattern being a silicon pattern; and
a second fin pattern, the second fin pattern including a second lower pattern and a second upper pattern, the second lower pattern and the second upper pattern being sequentially stacked on the compound semiconductor layer in the second region such that the second upper pattern is directly on the second lower pattern, the second fin pattern being a silicon germanium pattern, the first lower pattern and second lower pattern each being integral with the compound semiconductor layer and having a common material composition with a material composition of the compound semiconductor layer, the first upper pattern and the second upper pattern each being a separate and integral pattern, a germanium fraction of the second upper pattern being greater than a germanium fraction of the second lower pattern and the first lower pattern, and a width of the second upper pattern being different from a width of the first upper pattern, the first upper pattern and the second upper pattern each configured to be a channel region of a transistor,
wherein a width of the second upper pattern is different from a width of the second lower pattern at a boundary between the second upper pattern and the second lower pattern, such that a step difference is formed between a sidewall of a trench that defines the second upper pattern and a sidewall of the trench that defines the second lower pattern.

14. The semiconductor device of claim 13 ,

Assignees

• Choi Yong Joon
• Kwon Tae Yong
• Cantoro Mirco
• Yang Chang Jae
• Khang Dong Hoon
• Kim Woo Ram
• Kim Cheol
• Mun Seung Jin
• Ha Seung Mo
• Kim Do Hyoung
• Kim Seong Ju
• You So Ra
• Hong Woong Ki
• Samsung Electronics Co Ltd

Inventors

• Choi Yong-Joon
• Kwon Tae-Yong
• Cantoro Mirco
• Yang Chang-Jae
• KHANG Dong-Hoon
• KIM Woo-Ram
• Kim Cheol
• Mun Seung-Jin
• Ha Seung-Mo
• Kim Do-Hyoung
• Kim Seong-Ju
• YOU So-Ra
• Hong Woong-Ki

Classifications

• H01L27/0924 Primary

  Electricity · mapped topic

• H01L21/823821

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic

• H01L21/823431

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic