Semiconductor device and semiconductor package comprising the same

Patent metadata

Field	Value
Publication number	US-9966317-B2
Application number	US-201615298919-A
Country	US
Kind code	B2
Filing date	Oct 20, 2016
Priority date	Oct 21, 2015
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

A semiconductor device may include a first terminal electrically connected to a first semiconductor chip, a second terminal electrically connected to a second semiconductor chip, which is different from the first semiconductor chip, a first signal line electrically connecting the first terminal and the second terminal and including a first node, a third terminal connected to a tester monitoring a signal transmitted between the first semiconductor chip and the second semiconductor chip, a fourth terminal applied a reference voltage, a second signal line electrically connecting the third terminal and the fourth terminal and including a second node, a first resistor connected between the first node and the second node and a second resistor directly connected to the second node different from the first resistor.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first terminal electrically connected to a first semiconductor chip;
a second terminal electrically connected to a second semiconductor chip;
a first signal line configured to electrically connect the first terminal and the second terminal;
a third terminal configured to electrically connect to a tester, the tester configured to monitor a signal transmitted between the first semiconductor chip and the second semiconductor chip;
a second signal line configured to electrically connect the third terminal and a fourth terminal, the fourth terminal configured to receive a reference voltage;
a first resistor electrically connected between a first node and a second node, the first node being associated with the first signal line and the second node being associated with the second signal line; such that a first end of the first resistor is connected to the first node between the first semiconductor chip and the second semiconductor chip and a second end of the first resistor is connected to the tester via the second node; and
a second resistor electrically connected between the second node and the fourth terminal such that a first end of the second resistor is directly connected to the second node and a second end of the second resistor is connected to the fourth terminal.

2. The semiconductor device of claim 1 , further comprising:
an interposer configured to electrically connect the tester to the semiconductor device.

3. The semiconductor device of claim 1 , wherein the reference voltage is a power supply voltage.

4. The semiconductor device of claim 1 , wherein a sum of a resistance of resistor components of the tester and a resistance of the second resistor equals a resistance of the first resistor.

5. The semiconductor device of claim 1 , wherein the second resistor and the first resistor are connected in parallel to the second node.

6. A semiconductor package, comprising:
a circuit board including a reference voltage terminal configured to receive a reference voltage;
an interposer electrically connected to the circuit board, the interposer including a tester terminal; and
a first semiconductor chip on the interposer, the first semiconductor chip configured to electrically connect to the circuit board and the interposer, wherein the interposer includes,
a first wire configured to electrically connect the circuit board and the first semiconductor chip,
a second wire configured to electrically connect to the first wire, the second wire including a first resistor such that a first end of the first resistor is connected between the first semiconductor chip and the circuit board and a second end of the first resistor is connected to the tester terminal, and
a third wire configured to electrically connect the tester terminal and the reference voltage terminal, the third wire including a second resistor such that a first end of the second resistor is directly connected to the tester terminal and a second end of the second resistor is connected to the reference voltage terminal.

7. The semiconductor package of claim 6 , wherein the reference voltage is a power supply voltage.

8. The semiconductor package of claim 6 , wherein
the second wire includes a first region and a second region each having a different electrical conductivity, the second region having the first resistor associated therewith, and
the third wire includes a third region and a fourth region each having a different electrical conductivity, the fourth region having the second resistor associated therewith.

9. The semiconductor package of claim 8 , wherein the electrical conductivity of the second region differs from the electrical conductivity of the fourth region.

10. The semiconductor package of claim 8 , wherein
the electrical conductivity of the first region is higher than the electrical conductivity of the second region, and
the electrical conductivity of the third region is higher than the electrical conductivity of the fourth region.

11. The semiconductor package of claim 6 , wherein the second wire is electrically connected to the third wire.

12. The semiconductor package of claim 6 , further comprising:
a second semiconductor chip electrically connected to the circuit board and electrically isolated from the interposer, the second semiconductor chip electrically connected to the first wire.

13. The semiconductor package of claim 12 , wherein the tester terminal is configured to connect to a tester, the tester being configured to monitor a signal transmitted between the first semiconductor chip and the second semiconductor chip such that the signal is transmitted between the first semiconductor chip and the second semiconductor chip via a first signal path through the first wire that is connected to the second wire, the tester is configured to receive the signal via a second signal path through the second wire including the first resistor, and the second resistor included in the third wire is connected between the second signal path and the reference voltage terminal.

14. The semiconductor package of claim 6 , wherein
the first wire electrically connects a first terminal associated with the first semiconductor chip and a second terminal associated with the circuit board,
the first semiconductor chip is electrically connected to the interposer via the first terminal, and
the circuit board is electrically connected to the interposer via the second terminal.

15. The semiconductor package of claim 13 , wherein a sum of a resistance of resistor components of the tester and a resistance of the second resistor equals a resistance of the first resistor.

16. A semiconductor device comprising:
an interposer configured to electrically connect a testing device to a first signal path between a first semiconductor chip and a second semiconductor chip, the testing device configured to monitor a signal transmitted via the first signal path between the first semiconductor chip and the second semiconductor chip, the interposer including,
a first resistor configured to electrically connect a first node and a second node, the first node being a node on the first signal path between the first semiconductor chip and the second semiconductor chip and the second node being a node on a second signal path between the first node and the testing device such that a first end of the resistor is connected to the first node between the first semiconductor chip and the second semiconductor chip and a second end of the first resistor is connected to the testing device via the second node, and
a second resistor configured to electrical connect a reference terminal and the second node such that a first end of the second resistor is directly connected to the second node and a second end of the second resistor is connected to the reference terminal, the reference terminal configured to receive a reference voltage.

17. The semiconductor device of claim 16 , wherein the first signal path includes a first line configured to electrically connect the first semiconductor chip and the second semiconductor chip and the second signal path includes a second line and a third line, the second line configured to electrically connect the first node and the second node, and the third line configured to electrically connect the testing device to the second node.

18. The semiconductor device of claim 17 , wherein the first line is configured to electrically connect the first semiconductor chip and a circuit board having the second semiconductor chip thereon

Assignees

• Kim Joung Yeal
• Kwon Dae Hyun
• Woo Mi Young
• Yoon Joon Sun
• Choi Jong Hyun
• Samsung Electronics Co Ltd

Inventors

• Kim Joung-Yeal
• Kwon Dae-Hyun
• Woo Mi-Young
• Yoon Joon-Sun
• Choi Jong-Hyun

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10P74/273 Primary

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H01L28/20

  Electricity · mapped topic

• H01L27/0802

  Electricity · mapped topic