Forming nanotips

Patent metadata

Field	Value
Publication number	US-9966253-B2
Application number	US-201615054005-A
Country	US
Kind code	B2
Filing date	Feb 25, 2016
Priority date	Feb 25, 2016
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

A nanotip apparatus which includes nanotips arranged in a pattern on a semiconductor base. Each of the nanotips have a pointed tip portion and a base portion in contact with the semiconductor base. Further, each of the nanotips include a gradient of silicon germanium (SiGe) with the highest concentration of germanium being at the pointed tip portion and the lowest concentration of germanium being at the base in contact with the semiconductor base. Also disclosed is a method in which the nanotips may be formed.

First claim

What is claimed is:

1. A nanotip apparatus comprising a plurality of nanotips arranged in a pattern on a semiconductor base, each of the nanotips having a pointed tip and having a base portion in contact with the semiconductor base, each of the nanotips further comprising a gradient of silicon germanium (SiGe) extending continuously from the pointed tip to the semiconductor base with the highest concentration of germanium being at the pointed tip and the lowest concentration of germanium being at the base portion in contact with the semiconductor base.

2. The apparatus of claim 1 wherein the nanotips having a cone shape.

3. The apparatus of claim 1 wherein the nanotips having a pyramidal shape.

4. The apparatus of claim 1 wherein the plurality of nanotips are doped to increase their conductivity.

5. The apparatus of claim 4 further comprising an anode electrode opposite to the nanotip field emitters and the semiconductor base, the combination of the anode electrode, nanotip field emitters and the semiconductor base forming a field emitter.

6. The apparatus of claim 1 wherein the semiconductor base is a plurality of cantilevers with at least one nanotip field emitter on each nanotip and further comprising a semiconductor substrate joined to the plurality of cantilevers.

7. A method comprising:
forming a substrate comprising a silicon germanium (SiGe) gradient layer on a semiconductor base such that there is a greater concentration of germanium at a top of the SiGe layer away from the semiconductor base than at a bottom of the SiGe layer in contact with the semiconductor base;
patterning the SiGe gradient layer to form SiGe pillars;
depositing an oxide layer over and between the SiGe pillars; and
oxidizing the SiGe pillars such that a top of the SiGe pillars is oxidized faster than a bottom of the SiGe pillars in contact with the silicon base, the oxidizing causing the silicon in the SiGe pillars to react with oxygen to form an oxide and be partially removed from the SiGe pillars such that tapered SiGe pillars are formed with the top of the SiGe pillars forming a tip and having a greater concentration of germanium at the tip than at the bottom of the pillars.

8. The method of claim 7 wherein forming a substrate comprising a silicon germanium (SiGe) gradient layer on a semiconductor base comprises:
forming a substrate comprising a SiGe layer on the semiconductor base; and
thermally annealing the substrate to create the SiGe gradient layer.

9. The method of claim 8 wherein the process of thermally annealing is conducted in an inert environment such that a concentration of germanium at the tip of the SiGe pillars is less than the concentration of germanium in the tip prior to thermally annealing.

10. The method of claim 8 wherein the process of thermally annealing is conducted in an oxidation environment such that a concentration of germanium at the tip of the SiGe pillars is greater than the concentration of germanium in the tip prior to thermally annealing.

11. The method of claim 7 wherein forming a substrate comprising a silicon germanium (SiGe) gradient layer on a semiconductor base comprises:
depositing the SiGe gradient layer by a phased deposition process in which silicon is initially deposited followed by gradually increasing the amount of germanium deposited while gradually decreasing the amount of silicon deposited until the SiGe gradient layer is formed.

12. The method of claim 7 wherein in the process of patterning the SiGe layer to form SiGe pillars, the SiGe pillars formed are truncated pyramids.

13. The method of claim 12 wherein in the process of oxidizing, the SiGe pillars formed after oxidizing are pyramids.

14. The method of claim 7 wherein in the process of patterning the SiGe layer to form SiGe pillars, the SiGe pillars formed are cylinders.

15. The method of claim 14 wherein in the process of oxidizing, the SiGe pillars formed after oxidizing are cones.

16. The method of claim 8 further comprising epitaxially depositing the SiGe layer on the silicon base.

17. A method comprising:
forming a substrate comprising an array of SiGe pillars on a semiconductor substrate, the SiGe pillars having a germanium gradient within the SiGe pillars such that there is a greater concentration of germanium at a top of the SiGe pillars away from the semiconductor base than at a bottom of the SiGe pillars in contact with the semiconductor base; and
oxidizing the SiGe pillars such that tapered SiGe pillars are formed with the top of the SiGe pillars forming a tip and having a greater concentration of germanium at the tip than at the bottom of the pillars.

18. The method of claim 17 wherein in the process of oxidizing, the SiGe pillars formed after oxidizing are pyramids.

19. The method of claim 17 wherein in the process of oxidizing, the SiGe pillars formed after oxidizing are cones.

20. The method of claim 17 wherein oxidizing the SiGe pillars includes oxidizing the SiGe pillars such that a top of the SiGe pillars is oxidized faster than a bottom of the SiGe pillars in contact with the silicon base, the oxidizing causing the silicon in the SiGe pillars to be partially removed from the SiGe pillars such that tapered SiGe pillars are formed with the top of the SiGe pillars forming the tip.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Divakaruni Ramachandra
• Li Juntao
• Mochizuki Shogo

Classifications

• H10P14/6308 Primary

  of Group IV semiconductors · CPC title

• G01Q70/14

  Particular materials · CPC title

• H01L21/02236 Primary

  Electricity · mapped topic

• G01Q70/16

  Probe manufacture · CPC title

• H01J9/025 Primary

  of field emission cathodes · CPC title