Determining read voltages for a storage device

Patent metadata

Field	Value
Publication number	US-9966147-B1
Application number	US-201715675992-A
Country	US
Kind code	B1
Filing date	Aug 14, 2017
Priority date	Aug 14, 2017
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

Systems and methods presented herein provide for computing read voltages for a storage device. In one embodiment, a controller is controller is operable to soft read data from a portion of the storage device, and to iteratively test the soft read data a predetermined number of times. For example, the controller may test the soft read data a number of times by applying a different probability weight to the soft read data each time the soft read data is tested. The controller may then decode the soft read data based on the probability weight, and determine an error metric of the decoded soft read data. Then, the controller determines a read voltage for the portion of the storage device based on the probability weight and the error metric.

First claim

What is claimed is:

1. A storage system, comprising:
a storage device; and
a controller operable to soft read data from a portion of the storage device, and to iteratively test the soft read data a predetermined number of times, the controller being operable to iteratively test the soft read data by:
applying a probability weight to the soft read data;
decoding the soft read data based on the probability weight; and
determining an error metric of the decoded soft read data,

the controller being further operable to determine a read voltage for the portion of the storage device based on the probability weight and the error metric.

2. The storage system of claim 1 , wherein:
the controller is further operable to decode the soft read data using a low density parity check (LDPC).

3. The storage system of claim 1 , wherein:
the storage device is a NAND flash memory device, a magnetoresistive random-access memory device, or a combination thereof.

4. The storage system of claim 1 , wherein:
the controller is further operable to perform said soft reading, iterative testing, and determining a read voltage a plurality of times, and to statistically track the read voltage in response to said performing to determine a longevity of the portion of the storage device.

5. The storage system of claim 4 , wherein:
the controller is further operable to retire the portion of the storage device when the portion of the storage device has passed its longevity.

6. The storage system of claim 4 , wherein:
the controller is further operable to select another probability weight based on the statistically tracked read voltage.

7. The storage system of claim 1 , wherein:
the probability weight is a log likelihood ratio (LLR) weight.

8. A method operable with a storage device, the method comprising:
soft reading data from a portion of the storage device;
iteratively testing the soft read data a predetermined number of times, said iterative testing comprising:
applying a probability weight to the soft read data;
decoding the soft read data based on the probability weight; and
determining an error metric of the decoded soft read data; and

determining a read voltage for the portion of the storage device based on the probability weight and the error metric.

9. The method of claim 8 , wherein:
decoding comprises using a low density parity check (LDPC) to decode the soft read data.

10. The method of claim 8 , wherein:
the storage device is a NAND flash memory device, a magnetoresistive random-access memory device, or a combination thereof.

11. The method of claim 8 , further comprising:
performing said soft reading, iterative testing, and determining a read voltage a plurality of times; and
statistically tracking the read voltage in response to said performing to determine a longevity of the portion of the storage device.

12. The method of claim 11 , further comprising:
retiring the portion of the storage device when the portion of the storage device has passed its longevity.

13. The method of claim 11 , further comprising:
selecting another probability weight based on the statistically tracked read voltage.

14. The method of claim 8 , wherein:
the probability weight is a log likelihood ratio (LLR) weight.

15. A non-transitory computer readable medium comprising instructions that, when executed by a controller operable with a storage device, direct the controller to:
soft read data from a portion of the storage device;
iteratively test the soft read data a predetermined number of times, said iterative testing comprising:
apply a probability weight to the soft read data;
decode the soft read data based on the probability weight; and
determine an error metric of the decoded soft read data; and

determine a read voltage for the portion of the storage device based on the probability weight and the error metric.

16. The computer readable medium of claim 15 , further comprising instructions that direct the controller to:
decode comprises using a low density parity check (LDPC) to decode the soft read data.

17. The computer readable medium of claim 15 , wherein:
the storage device is a NAND flash memory device, a magnetoresistive random-access memory device, or a combination thereof.

18. The computer readable medium of claim 15 , further comprising instructions that direct the controller to:
perform said soft reading, iterative testing, and determining a read voltage a plurality of times; and
statistically track the read voltage in response to said performing to determine a longevity of the portion of the storage device.

19. The computer readable medium of claim 18 , further comprising instructions that direct the controller to:
retire the portion of the storage device when the portion of the storage device has passed its longevity.

20. The computer readable medium of claim 18 , further comprising instructions that direct the controller to:
select another probability weight based on the statistically tracked read voltage,
wherein the probability weight is a log likelihood ratio (LLR) weight.

Assignees

• Seagate Technology Llc
• Seagate Technology

Inventors

• Lien Nicholas Odin
• Goss Ryan James

Classifications

• G11C29/76

  using address translation or modifications · CPC title

• G11C29/4401

  for self repair · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C11/005

  comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title