Fractional program commands for memory devices

Patent metadata

Field	Value
Publication number	US-9966142-B2
Application number	US-99094509-A
Country	US
Kind code	B2
Filing date	May 6, 2009
Priority date	May 13, 2008
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

A memory system ( 100 B) includes an array of non-volatile memory cells ( 140 ) and a memory controller ( 110 ) having a first port (port connected to line 101 ) to receive a program command that addresses a number of the memory cells for a programming operation, having a second port (port connected to lines 102 and 103 ) coupled to the memory array via a command pipeline, and configured to create a plurality of fractional program commands in response to the program command. Execution of each fractional program command applies a single program pulse to the addressed memory cells to incrementally program the addressed memory cells with program data, where the duration of the program pulse associated with each fractional program command is a selected fraction of the total programming time typically required to program the memory cells.

First claim

What is claimed is:

1. A memory system comprising:
a memory device including an array of non-volatile memory cells; and
a memory controller having a first port to receive a program command that addresses a number of the memory cells for a programming operation, having a second port coupled to the memory device via a command pipeline, and configured to create a plurality of independent fractional program commands in response to the program command, wherein each of the fractional program commands includes a verify operation, wherein the memory controller is further configured to selectively insert a non-program command into the command pipeline ahead of a selected number of the fractional program commands, and wherein programming each of the addressed memory cells involves executing multiple fractional program commands.

2. The memory system of claim 1 , wherein each fractional program command applies a single program pulse to selected memory cells, and wherein a duration of each program pulse is a selected fraction of a total programming time required to program the memory cells with the program data.

3. The memory system of claim 2 , wherein the program command includes a pulse width value that determines the duration of the program pulse associated with each of the fractional program commands.

4. The memory system of claim 1 , wherein the program command includes a limit value that specifies a maximum number of fractional program commands created by the memory controller.

5. The memory system of claim 1 , wherein the non-program command is executed in the memory device while the programming operation is in progress without interrupting execution of any of the fractional program commands.

6. The memory system of claim 1 , wherein the non-program command comprises a read command.

7. The memory system of claim 1 , wherein the memory controller further comprises:
a command queue for storing the plurality of fractional program commands.

8. The memory system of claim 7 , wherein the memory controller is configured to selectively insert a non-program command ahead of a selected number of the fractional program commands previously queued in the command queue.

9. The memory system of claim 8 , wherein the memory controller further comprises:
a program address register for storing the addresses of memory cells being programmed during the programming operation; and
a control circuit for comparing an address associated with the non-program command with the program addresses stored in the program address register, wherein the control circuit selectively forwards the non-program command to the command queue in response to the comparing.

10. The memory system of claim 9 , wherein the control circuit forwards the non-program command to the command queue if the address associated with the non-program command does not match any of the program addresses stored in the program address register.

11. The memory system of claim 1 , further comprising:
a mode register for storing mode data indicative of a programming mode.

12. The memory system of claim 11 , wherein the memory controller generates the fractional program commands in response to the program command if the mode data is in a first state, and initiates a sequence of program-verify cycles in response to the program command if the mode data is in a second state.

13. A method of programming data into a memory device including an array of memory cells, the method comprising:
receiving a program command that addresses a number of the memory cells for a programming operation to program data therein;
creating a plurality of independent fractional program commands in response to the program command, wherein each of the fractional program commands includes a verify operation to generate verify data indicating whether the addressed memory cells are properly programmed,
selectively inserting a non-program command into the command pipeline ahead of a selected number of the fractional program commands; and
selectively forwarding the fractional program commands to the memory device for execution, wherein programming each of the addressed memory cells involves executing multiple fractional program commands.

14. The method of claim 13 , further comprising:
queuing the fractional program commands in a command queue.

15. The method of claim 14 , wherein the non-program command comprises a read command, and wherein the method further comprises:
executing the non-program command in the memory device prior to executing the selected number of fractional program commands.

16. The method of claim 13 , wherein the selectively inserting comprises:
storing the program addresses identified by the program command in a program address register;
comparing an address associated with the non-program command with the program addresses stored in the program address register; and
queuing the non-program command in the command queue if the address associated with the non-program command does not match any of the program addresses.

17. The method of claim 16 , further comprising:
if the verify data indicates that all the addressed memory cells are properly programmed, removing the corresponding program address from the program address register; and
if the verify data identifies some of the addressed memory cells that have not been completely programmed, sending the next fractional program command to the array to further program the identified memory cells.

18. The method of claim 13 , further comprising:
selectively forwarding the non-program command to the memory device for execution while the programming operation is in progress without interrupting the execution of any of the fractional program commands.

19. The method of claim 18 , wherein the selectively forwarding comprises:
comparing an address associated with the non-program command with the program addresses identified by the program command; and
immediately forwarding the non-program command to the memory device if the address associated with the non-program command does not match the program addresses.

20. The method of claim 13 , wherein each fractional program command applies a single program pulse to selected memory cells, and wherein a duration of each program pulse is a selected fraction of a total time of the programming operation.

21. The method of claim 20 , further comprising:
providing a pulse width value along with the program command; and
selectively adjusting the duration of the program pulse associated with each fractional program command in response to the pulse width value.

22. The method of claim 13 , further comprising:
providing a limit value along with the program command; and
limiting the number of fractional program commands executed in the memory device in response to the limit value.

23. The method of claim 13 , further comprising, for each fractional program command:
generating verify data that indicates whether the corresponding fractional program command completely programs the program data into the addressed memory cells; and
selectively executing a next fractional program command in the memory device in response to the verify data.

24. A flash memory device comprising:
an array of non-volatile memory cells; and
a control circuit having a first port to receive a program command that addresses a number of the memory cells for a programming operation, having a second port coupled to the array of memory cells

Assignees

• Haukness Brent S
• Shaeffer Ian
• Bronner Gary B
• Rambus Inc

Inventors

• Haukness Brent S
• Shaeffer Ian
• Bronner Gary B

Classifications

• G06F2212/7204

  Capacity control, e.g. partitioning, end-of-life degradation · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0611

  in relation to response time · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title