Accommodating engineering change orders in integrated circuit design

Patent metadata

Field	Value
Publication number	US-9965576-B2
Application number	US-201715656077-A
Country	US
Kind code	B2
Filing date	Jul 21, 2017
Priority date	May 3, 2016
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

A method includes receiving a register-transfer-level description and a gate-level description for an integrated circuit design. The gate-level description includes one or more spare latches implemented as reconfigurable latch filler cells. The method further includes receiving an engineering change order, and, responsive to the engineering change order, adding the at least one additional latch to the register-transfer-level description and, for at least one of the at least one additional latch, selecting one of the one or more spare latches in the register-transfer-level description to yield a selected spare latch. The method further includes, for the selected spare latch, identifying a selected reconfigurable latch filler cell in the gate-level description and replacing the selected reconfigurable latch filler cell with an operational latch in the gate-level description. The method further includes finalizing the integrated circuit design. A corresponding computer program product and computer systems are also disclosed.

First claim

What is claimed is:

1. A computer-implemented method, comprising:
receiving a register-transfer-level description and a gate-level description for an integrated circuit design, wherein said gate-level description comprises one or more spare latches implemented as reconfigurable latch filler cells;
receiving an engineering change order for said integrated circuit design, wherein said engineering change order requires at least one additional latch;
responsive to said engineering change order, adding said at least one additional latch to said register-transfer-level description;
for at least one of said at least one additional latch, selecting one of said one or more spare latches in said register-transfer-level description to yield a selected spare latch;
for said selected spare latch, identifying a selected reconfigurable latch filler cell in said gate-level description;
replacing said selected reconfigurable latch filler cell with an operational latch in said gate-level description; and
finalizing said integrated circuit design;
wherein at least one said reconfigurable latch filler comprises a scan input connection connected to a scan output connection by a short;
wherein replacing said selected reconfigurable latch filler cell with an operational latch in said gate-level description comprises removing said short;
wherein said reconfigurable latch filler cell comprises at least one disconnection from a power rail;
wherein replacing said selected reconfigurable latch filler cell with an operational latch in said gate-level description comprises connecting said reconfigurable latch filler cell to said power rail;
wherein said reconfigurable latch filler cell comprises at least one disconnection from a clock pin;
wherein replacing said selected reconfigurable latch filler cell with an operational latch in said gate-level description comprises connecting said reconfigurable latch filler cell to said clock pin;
wherein said computer-implemented method further comprises generating a netlist from said gate-level description, routing said engineering change order based on said netlist, and omitting re-ordering a scan chain for said integrated circuit design;
wherein said computer-implemented method further comprises identifying one or more clock buffers for said integrated circuit design, said one or more clock buffers having been sized for said one or more spare latches, and reducing said one or more clock buffers to an optimized clock buffer size, based on a number of instantiated latches in said integrated circuit design; and
wherein said operational latch is identical in area footprint to an pin-compatible with an originally designed latch.

Assignees

• IBM

Inventors

• Datta Ayan
• Gupta Saurabh
• Udhayakumar Jayaprakash
• Veerabhadraiah Rajesh
• Verma Alok

Classifications

• G06F2119/08

  Thermal analysis or thermal optimisation · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G06F30/34

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title