Dynamic clock lane assignment for increased performance and security

Patent metadata

Field	Value
Publication number	US-9965438-B2
Application number	US-201514968166-A
Country	US
Kind code	B2
Filing date	Dec 14, 2015
Priority date	Dec 14, 2015
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

A lane within a processor bus that communicatively connects a transmitter and a receiver is dynamically assigned as a clock lane. The clock lane subsequently transmits a reference clock signal to coordinate data communications from the transmitter to the receiver. The clock lane may be assigned by determining signal margins of various lanes of the processor bus. The signal margins are determined by the transmitter sending a test pattern upon the various lanes and analyzing the received test pattern at the receiver. A dynamically assigned clock lane results increased overall signal integrity of communications between the transmitter and receiver. Further, a dynamically assigned clock lane may result in different lanes being assigned as the clock lane at distinct boot up instances, adding to the complexity of the unauthorized user determining the operational logic of the transmitter.

First claim

What is claimed is:

1. A computer program product for dynamically assigning a clock lane in a processor bus comprising a plurality of lanes that communicate signals from a transmitter to a receiver, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions readable by:
a transmitter to send a signal pattern upon each lane,
a receiver to receive the signal pattern upon each lane,
the receiver to determine a distortion from the received signal pattern associated with each lane,
the receiver to identify a particular lane associated with a minimum distortion, and
the transmitter to assign the particular lane associated with the minimum distortion as a clock lane that transmits a reference clock signal from the transmitter to the receiver in subsequent signal communications from the transfer to the receiver, wherein the reference clock signal is used to coordinate actions of a first digital circuit within the transmitter and a second digital circuit within the receiver.

2. The computer program product of claim 1 , wherein the program instructions that are readable by the receiver to determine the distortion from the received signal pattern associated with each lane further cause the receiver to generate an eye diagram associated with each lane from the received signal pattern.

3. The computer program product of claim 2 , wherein the program instructions that are readable by the receiver to identify the particular lane associated with the minimum distortion further cause the receiver to measuring an eye width of the eye diagram associated with each lane.

4. The computer program product of claim 3 , wherein the program instructions that are readable by the receiver to identify the particular lane associated with the minimum distortion further cause the receiver to identify the lane associated with the widest eye as the particular lane associated with the minimum distortion.

5. The computer program product of claim 4 , wherein the processor bus comprises an additional lane than is necessary for the bus to communicate a predetermined data width from the transmitter to the receiver.

6. The computer program product of claim 5 , wherein the program instructions are further readable by the transmitter to assign the lane associated with the narrowest eye as an inactive lane that does not transmit signals from the transmitter to the receiver in subsequent signal communications from the transfer to the receiver.

7. The computer program product of claim 1 , wherein the program instructions are further readable by the transmitter to assign a first lane within the processor bus as the particular lane that transmits the clock signal from the transmitter to the receiver at a first transmitter and receiver boot instance and are subsequently readable by the transmitter to assign a second lane within the processor bus as the particular lane that transmits the clock signal from the transmitter to the receiver at a second transmitter and receiver boot instance.

Assignees

• IBM

Inventors

• Bartley Gerald K
• Becker Darryl J
• Doyle Matthew S
• Jeanson Mark J
• Maxson Mark O

Classifications

• G06F13/4291 Primary

  using a clocked protocol · CPC title

• G06F11/1428

  with loss of hardware functionality · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/4018

  with data-width conversion · CPC title