Communication low-speed and high-speed parallel bit streams over a high-speed serial bus

Patent metadata

Field	Value
Publication number	US-9965435-B2
Application number	US-201514939020-A
Country	US
Kind code	B2
Filing date	Nov 12, 2015
Priority date	Nov 12, 2015
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

Aspects disclosed in the detailed description include communicating low-speed and high-speed parallel bit streams over a high-speed serial bus. In one aspect, a data transmitting circuit converts a low-speed parallel bit stream into a high-speed parallel bit stream and then serializes the converted high-speed parallel bit stream based on a high-speed reference frequency. In another aspect, a data receiving circuit recovers the low-speed parallel bit stream from the high-speed parallel bit stream if the low-speed parallel bit stream is determined to exist in the high-speed parallel bit stream. By serializing and deserializing the low-speed parallel bit stream based on the high-speed reference frequency, it is possible to communicate the high-speed parallel bit stream and the low-speed parallel bit stream over the high-speed serial bus without requiring additional serializers and deserializers, thus reducing component costs and implementation complexities in both the transmitting circuit and the receiving circuit.

First claim

What is claimed is:

1. A data transmitting circuit, comprising:
a serializer circuit configured to serialize a high-speed parallel bit stream corresponding to a high-speed bitrate based on a high-speed reference frequency to generate a high-speed serial bit stream for transmission over a high-speed serial bus, wherein the high-speed parallel bit stream comprises a plurality of binary bit periods, each of the plurality of binary bit periods comprising a first number of parallel binary bits; and
a data processing circuit configured to:
receive a low-speed parallel bit stream corresponding to a low-speed bitrate slower than the high-speed bitrate, wherein the low-speed parallel bit stream is a pulse width modulated (PWM) parallel bit stream comprising a plurality of PWM bit periods, each of the plurality of PWM bit periods comprising a second number of parallel PWM bits;
determine a bit multiplier value by dividing the high-speed bitrate by the low-speed bitrate; and
for each of the second number of parallel PWM bits in each of the plurality of PWM bit periods:
encode the PWM bit into a calculated number of binary bit periods among the plurality of binary bit periods in the high-speed parallel bit stream based on the bit multiplier value and a predefined PWM bit format, wherein the calculated number of binary bit periods is determined by dividing the bit multiplier value by the first number of parallel binary bits; and
output the calculated number of binary bit periods to the serializer circuit.

2. The data transmitting circuit of claim 1 , wherein the data processing circuit is further configured to receive the high-speed parallel bit stream and pass the received high-speed parallel bit stream to the serializer circuit.

3. The data transmitting circuit of claim 1 , wherein the high-speed reference frequency is a divisor of the high-speed bitrate.

4. The data transmitting circuit of claim 1 , wherein the data processing circuit is further configured to increase the bit multiplier value to an integer value that is a multiple of the first number of parallel binary bits if the bit multiplier value divided by the first number of parallel binary bits in each of the plurality of binary bit periods has a remainder.

5. The data transmitting circuit of claim 1 , wherein:
the first number of parallel binary bits in each of the plurality of binary bit periods is equal to ten binary bits; and
the second number of parallel PWM bits in each of the plurality of PWM bit periods is equal to twenty PWM bits.

6. The data transmitting circuit of claim 1 , wherein the high-speed serial bit stream is transmitted over a MIPI Alliance (MIPI) high-speed serial bus.

7. The data transmitting circuit of claim 1 provided in a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a mobile phone; a cellular phone; a smart phone; a tablet; a phablet; a computer; a portable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; and an automobile.

8. The data transmitting circuit of claim 3 , wherein a division of the high-speed bitrate by the low-speed bitrate has a remainder.

9. The data transmitting circuit of claim 6 , wherein the serializer circuit is configured to generate the high-speed serial bit stream for communication over a MIPI M-PHY bus.

10. The data transmitting circuit of claim 6 , wherein the serializer circuit is configured to generate the high-speed serial bit stream for communication over a MIPI C-PHY bus.

11. A method for transmitting a low-speed parallel bit stream over a high-speed serial bus, comprising:
receiving the low-speed parallel bit stream corresponding to a low-speed bitrate, wherein the low-speed parallel bit stream is a pulse width modulated (PWM) parallel bit stream comprising a plurality of PWM bit periods, each of the plurality of PWM bit periods comprising a second number of parallel PWM bits;
determining a bit multiplier value by dividing a high-speed bitrate by the low-speed bitrate;
for each of the second number of parallel PWM bits in each of the plurality of PWM bit periods:
encoding the PWM bit into a calculated number of binary bit periods among a plurality of binary bit periods in a high-speed parallel bit stream based on the bit multiplier value and a predefined PWM bit format, wherein the calculated number of binary bit periods is determined by dividing the bit multiplier value by a first number of parallel binary bits; and
outputting the calculated number of binary bit periods to a serializer circuit in the converted high-speed parallel bit stream; and

serializing the converted high-speed parallel bit stream based on a high-speed reference frequency to generate a high-speed serial bit stream for transmission over the high-speed serial bus.

12. The method of claim 11 , further comprising:
receiving the high-speed parallel bit stream; and
serializing the received high-speed parallel bit stream to generate the high-speed serial bit stream for transmission over the high-speed serial bus.

13. A data receiving circuit, comprising:
a deserializer circuit configured to deserialize a high-speed serial bit stream received over a high-speed serial bus based on a high-speed reference frequency to generate a high-speed parallel bit stream corresponding to a high-speed bitrate, wherein the high-speed parallel bit stream comprises a plurality of binary bit periods, each of the plurality of binary bit periods comprising a first number of parallel binary bits; and
a data processing circuit configured to:
determine whether a pulse width modulated (PWM) parallel bit stream corresponding to a low-speed bitrate slower than the high-speed bitrate exists in the high-speed parallel bit stream; and
in response to determining that the PWM parallel bit stream exists in the high-speed parallel bit stream, for each of the plurality of binary bit periods in the high-speed parallel bit stream:
receive the first number of parallel binary bits;
detect a falling edge and a rising edge among the received first number of parallel binary bits;
count a number of binary ones in the received first number of parallel binary bits before the falling edge and a number of binary zeros in the received first number of parallel binary bits between the falling edge and the rising edge;
determine whether the received first number of parallel binary bits represents a PWM bit based on the counted number of binary zeros, the counted number of binary ones, and a predefined PWM bit format that distinctively defines a valid PWM bit; and
provide the determined PWM bit to a PWM deserializer in the data processing circuit.

14. The data receiving circuit of claim 13 , wherein the high-speed reference frequency is a divisor of the high-speed bitrate.

15. The data receiving circuit of claim 13 , wherein the deserializer circuit is configured to deserialize the high-speed serial bit stream received over a MIPI Alliance (MIPI) high-speed serial bus.

16. The data receiving circuit of claim 13 provided in a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a mobile phone; a cellular phone; a

Assignees

• Qualcomm Inc

Inventors

• Ladd William Knox
• Spears Kevin Wayne
• Vilas Mark Wesley
• Zhu Zhi

Classifications

• H03M9/00

  Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) · CPC title

• G06F13/4027

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/362

  with centralised access control · CPC title