Method for application-aware interrupts management

Patent metadata

Field	Value
Publication number	US-9965412-B2
Application number	US-201514970293-A
Country	US
Kind code	B2
Filing date	Dec 15, 2015
Priority date	Oct 8, 2015
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

According to one embodiment, a computer system includes a host computer, and a storage device coupled to the host computer. The host computer has a user-space device driver of the storage device in a user space of a host operating system (OS). The user-space device driver is configured to handle I/O operations to and from the storage device based on an application running on the host computer.

First claim

What is claimed is:

1. A computer system comprising:
a host computer comprising a plurality of central processing unit (CPU) cores; and
a storage device coupled to the host computer,
wherein the host computer has a user-space device driver of the storage device in a user space of a host operating system (OS), and
wherein the user-space device driver is configured to handle I/O operations to and from the storage device based on an application running on the host computer,
wherein the user-space device driver is configured to provide a first level interrupt coalescing in the storage device and a second level interrupt coalescing between the plurality of CPU cores and I/O queues in the user space.

2. The computer system of claim 1 further comprising: data storage, a description storage, and a configuration storage.

3. The computer system of claim 1 , wherein the storage device is a key-value (KV) device, and the user-space device driver is a KV device driver configured to run in the user space.

4. The computer system of claim 1 , wherein the user-space device driver comprise a user-space interrupt handler is configured to provide a thread CPU affinity between a thread of an application running in the user space and a first CPU core.

5. The computer system of claim 4 , wherein the host operating system further comprises a kernel interrupt handler that is configured to provide an interrupt CPU affinity between an I/O queue and an interrupt message handler.

6. The computer system of claim 5 , wherein the user-space device driver is configured to receive an interrupt from the KV device and identify that the interrupt is dedicated to the thread of the application running in the user space and the first CPU core via the interrupt CPU affinity and the thread CPU affinity.

7. The computer system of claim 6 , wherein the user-space device driver is configured to switch the interrupt to a second CPU core in a same socket as the first CPU core.

8. The computer system of claim 1 , wherein the storage device issues an interrupt message to an interrupt message handler among a plurality of interrupt message handlers based on the first level interrupt coalescing in the storage device and performs the second level interrupt coalescing at the user-space device driver.

9. The computer system of claim 1 , wherein the user-space device driver is configured to switch a mode of interrupt handling between an interrupt mode and a polling mode.

10. The computer system of claim 9 , wherein the user-space device driver is configured to monitor a local workload of a CPU core among the plurality of CPU cores and switch the mode of interrupt handling based on the local workload of the CPU core.

11. The computer system of claim 9 , wherein the user-space device driver is configured to monitor a global workload of the plurality of CPU cores and switch the mode of interrupt handling based on the global workload of the plurality of CPU cores.

12. A method for providing interrupt handling comprising:
providing a user-space device driver for a storage device coupled to a host computer in a user space of a host operating system of the host computer; and
configuring the user-space device driver to handle I/O operations to and from the storage device based on an application running on the host computer,
wherein the host computer comprises a plurality of CPU cores, and
wherein the user-space device driver is configured to provide a first level interrupt coalescing in the storage device and a second level interrupt coalescing between the plurality of CPU cores and I/O queues in the user space.

13. The method of claim 12 , wherein the storage device is a key-value (KV) device, and the user-space device driver is a KV device driver configured to run in the user space.

14. The method of claim 12 further comprising: configuring a user-space interrupt handler of the user-space device driver and providing a thread CPU affinity between a thread of an application running in the user space and a first CPU core.

15. The method of claim 14 further comprising: configuring a kernel interrupt handler of the host operating system and providing an interrupt CPU affinity between an I/O queue and an interrupt message handler.

16. The method of claim 15 further comprising receiving an interrupt from the KV device and identifying that the interrupt is dedicated to the thread of the application running in the user space and the first CPU core via the interrupt CPU affinity and the thread CPU affinity.

17. The method of claim 16 further comprising switching the interrupt to a second CPU core in a same socket as the first CPU core.

18. The method of claim 12 further comprising issuing an interrupt message to an interrupt message handler among a plurality of interrupt message handlers based on the first level interrupt coalescing in the storage device and performing the second level interrupt coalescing at the user-space driver.

19. The method of claim 15 further comprising switching a mode of interrupt handling between an interrupt mode and a polling mode.

20. The method of claim 19 further comprising monitoring a workload of the plurality of CPU cores and switching the mode of interrupt handling based on the workload of the plurality of CPU cores.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Liu Fei
• Ki Yang Seok
• Sun Xiling

Classifications

• G06F13/22

  using successive scanning, e.g. polling (G06F13/24 takes precedence) · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F16/28

  Databases characterised by their database models, e.g. relational or object models · CPC title

• G06F9/545 Primary

  where tasks reside in different layers, e.g. user- and kernel-space · CPC title