Processor with transactional capability and logging circuitry to report transactional operations

Patent metadata

Field	Value
Publication number	US-9965320-B2
Application number	US-201314142475-A
Country	US
Kind code	B2
Filing date	Dec 27, 2013
Priority date	Dec 27, 2013
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

A processor is described comprising memory access conflict detection circuitry to identify a conflict pertaining to a transaction being executed by a thread that believes it has locked information within a memory. The processor also includes logging circuitry to construct and report out a packet if the memory access conflict detection circuitry identifies a conflict that causes the transaction to be aborted.

First claim

We claim:

1. A method comprising:
identifying a conflict pertaining to a transaction being executed by a thread; and
constructing and reporting out a packet when identifying a conflict that causes an abort of said transaction, wherein the packet includes content that describes a reason for the abort of the transaction, the packet format includes a field to indicate any of a transaction start, a transaction end, and the abort, and the content is reported in response to the abort;
reporting out a second packet when detecting a memory race;
decoding a first instruction into a decoded first instruction;
executing the decoded first instruction to mark a beginning of a transaction;
reporting out a third packet when the decoded first instruction is executed;
decoding a second instruction into a decoded second instruction;
executing the decoded second instruction to mark an end of a transaction; and
reporting out a fourth packet when the decoded second instruction is executed.

2. The method of claim 1 wherein the reason is an abort from an overflow.

3. The method of claim 1 wherein said content indicates whether an aborted transaction is nested.

4. The method of claim 1 further comprising executing an instruction that explicitly aborts a transaction, wherein the reason indicates the abort is from the instruction.

5. The method of claim 1 wherein the content indicates whether the transaction may succeed on a retry.

6. The method of claim 1 wherein both the identifying the conflict that causes the abort of said transaction and the detecting the memory race are false positives.

7. The method of claim 1 wherein the identifying the conflict that causes the abort of said transaction is a false positive.

8. The method of claim 1 wherein the detecting the memory race is a false positive.

9. The method of claim 1 wherein the reason is an abort from a debug breakpoint.

10. A processor comprising:
memory access conflict detection circuitry to identify a conflict pertaining to a transaction being executed by a thread;
logging circuitry to construct and report out a packet if said memory access conflict detection circuitry identifies a conflict that causes an abort of said transaction, wherein the packet includes content that describes a reason for the abort of the transaction, the packet format includes a field to indicate any of a transaction start, a transaction end, and the abort, and the content is reported to the logging circuitry in response to the abort; and
a memory race detection circuit to detect memory races, said logging circuitry to construct and report out a second packet if said memory race detection circuit detects a memory race, wherein said processor is to permit said logging circuitry to be concurrently responsive to both said memory access conflict detection circuitry and said memory race detection circuit, said processor supports a first instruction that marks a beginning of a transaction, said logging circuitry to report out a third packet if said first instruction is executed, and said processor supports a second instruction that marks an end of a successfully completed transaction, said logging circuitry to report out a fourth packet if said second instruction that marks the end is executed.

11. The processor of claim 10 wherein the reason is an abort from an overflow.

12. The processor of claim 10 wherein said content indicates whether an aborted transaction is nested.

13. The processor of claim 10 wherein said processor supports an instruction that explicitly aborts a transaction, and the reason indicates the abort is from the instruction.

14. The processor of claim 10 wherein the content indicates whether the transaction may succeed on a retry.

15. The processor of claim 10 wherein both said memory access conflict detection circuitry and said memory race detection circuit are capable of generating false positives.

16. The processor of claim 10 wherein said memory access conflict detection circuitry is capable of generating false positives.

17. The processor of claim 10 wherein said memory race detection circuit is capable of generating false positives.

18. The processor of claim 10 wherein the reason is an abort from a debug breakpoint.

19. A computing system comprising:
a processor;
memory access conflict detection circuitry to identify a conflict pertaining to a transaction being executed by a thread on information within a memory;
logging circuitry to construct and report out a packet if said memory access conflict detection circuitry identifies a conflict that causes an abort of said transaction wherein the packet includes content that describes a reason for the abort of the transaction, the packet format includes a field to indicate any of a transaction start, a transaction end, and the abort, and the content is reported to the logging circuitry in response to the abort;
a memory controller coupled to said memory; and
a memory race detection circuit to detect memory races, said logging circuitry to construct and report out a second packet if said memory race detection circuit detects a memory race, wherein said processor is to permit said logging circuitry to be concurrently responsive to both said memory access conflict detection circuitry and said memory race detection circuit, said processor supports a first instruction that marks a beginning of a transaction, said logging circuitry to report out a third packet if said first instruction is executed, and said processor supports a second instruction that marks an end of a successfully completed transaction, said logging circuitry to report out a fourth packet if said second instruction that marks the end is executed.

20. The computing system of claim 19 wherein said processor supports an instruction that explicitly aborts a transaction, and the reason indicates the abort is from the instruction.

21. The computing system of claim 19 wherein the reason is an abort from an overflow.

22. The computing system of claim 19 wherein both said memory access conflict detection circuitry and said memory race detection circuit are capable of generating false positives.

23. The computing system of claim 19 wherein the reason is an abort from a debug breakpoint.

24. The computing system of claim 19 wherein the content indicates whether the transaction may succeed on a retry.

Assignees

• Intel Corp

Inventors

• Kassa Rolf
• Gottschlich Justin E
• Hu Shiliang
• Pokam Gilles A
• Knauerhase Robert C

Classifications

• G06F9/528 Primary

  by using speculative mechanisms · CPC title

• G06F9/467 Primary

  Transactional memory (G06F9/528 takes precedence) · CPC title

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F11/0724

  in a multiprocessor or a multi-core unit (multiprocessors per se G06F15/80) · CPC title

• G06F2212/251

  Local memory within processor subsystem · CPC title