Forced idling of memory subsystems

Patent metadata

Field	Value
Publication number	US-9965220-B2
Application number	US-201615016806-A
Country	US
Kind code	B2
Filing date	Feb 5, 2016
Priority date	Feb 5, 2016
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

First claim

What is claimed is:

1. A method for managing memory subsystems on a computing device, comprising:
receiving one or more memory access requests while a memory subsystem is in an active power mode;
determining whether the one or more memory access requests are initiated by a latency-critical process;
determining a period of time to force the memory subsystem on the computing device into a low power mode in response to determining that the one or more memory access requests are not initiated by a latency-critical process;
selecting the low power mode from a plurality of low power modes based on the determined period of time;
inhibiting memory access requests to the memory subsystem during the determined period of time;
forcing the memory subsystem into the low power mode for the determined period of time; and
executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

2. The method of claim 1 , wherein executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time comprises consecutively executing the memory access requests to the memory subsystem inhibited during the determined period of time.

3. The method of claim 1 , wherein determining the period of time to force the memory subsystem into the low power mode comprises:
monitoring a plurality of system variables of the computing device; and
determining the period of time based on the plurality of system variables.

4. The method of claim 3 , wherein the plurality of system variables include at least one of average bandwidth demand of the memory subsystem, input queue length of the memory subsystem, memory utilization during active periods of the memory subsystem, quality of service requirements, and stall cycles of one or more components accessing the memory subsystem.

5. The method of claim 1 , wherein determining the period of time to force the memory subsystem into the low power mode comprises:
determining an actual frequency at which the memory subsystem is clocked;
determining a frequency of a dynamic clock and voltage scaling unit in the computing device; and
determining the period of time based on the actual frequency and the frequency of the dynamic clock and voltage scaling unit.

6. The method of claim 1 , further comprising:
determining whether the latency-critical process is initiating memory access requests during the determined period of time; and
setting the memory subsystem in the active power mode in response to determining that a latency-critical process is initiating memory access requests during the determined period of time.

7. A computing device, comprising:
a memory subsystem; and
a processor coupled to the memory subsystem, and configured with processor-executable instructions to perform operations comprising:
receiving one or more memory access requests while the memory subsystem is in an active power mode;
determining whether the one or more memory access requests are initiated by a latency-critical process;
determining a period of time to force the memory subsystem into a low power mode in response to determining that the one or more memory access requests are not initiated by a latency-critical process;
selecting the low power mode from a plurality of low power modes based on the determined period of time;
inhibiting memory access requests to the memory subsystem during the determined period of time;
forcing the memory subsystem into the low power mode for the determined period of time; and
executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

8. The computing device of claim 7 , wherein the processor is further configured with processor-executable instructions to perform operations such that executing the memory access requests to the memory subsystem inhibited during the determined period of time comprises consecutively executing the memory access requests to the memory subsystem inhibited during the determined period of time.

9. The computing device of claim 7 , wherein the processor is further configured with processor-executable instructions to perform operations such that determining the period of time to force the memory subsystem into the low power mode comprises:
monitoring a plurality of system variables of the computing device; and
determining the period of time based on the plurality of system variables.

10. The computing device of claim 9 , wherein the plurality of system variables include at least one of average bandwidth demand of the memory subsystem, input queue length of the memory subsystem, memory utilization during active periods of the memory subsystem, quality of service requirements, and stall cycles of one or more components accessing the memory subsystem.

11. The computing device of claim 7 , wherein the processor is further configured with processor-executable instructions to perform operations such that determining the period of time to force the memory subsystem into the low power mode comprises:
determining an actual frequency at which the memory subsystem is clocked;
determining a frequency of a dynamic clock and voltage scaling unit in the computing device; and
determining the period of time based on the actual frequency and the frequency of the dynamic clock and voltage scaling unit.

12. The computing device of claim 7 , wherein the processor is configured with processor-executable instructions to perform operations further comprising:
determining whether a latency-critical process is initiating memory access requests during the determined period of time; and
setting the memory subsystem in the active power mode in response to determining that a latency-critical process is initiating memory access requests during the determined period of time.

13. A non-transitory computer readable storage medium having stored thereon processor-executable software instructions configured to cause a processor of a computing device to perform operations comprising:
receiving one or more memory access requests while the memory subsystem is in an active power mode;
determining whether the one or more memory access requests are initiated by a latency-critical process;
determining a period of time to force a memory subsystem on the computing device into a low power mode in response to determining that the one or more memory access requests are not initiated by a latency-critical process;
selecting the low power mode from a plurality of low power modes based on the determined period of time;
inhibiting memory access requests to the memory subsystem during the determined period of time;
forcing the memory subsystem into the low power mode for the determined period of time; and
executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

14. The non-transitory computer readable storage medium of claim 13 , wherein the stored processor-executable software instructions are configured to cause the processor to perform operations such that executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time comprises consecutively executing the memory access requests to the memory subsystem inhibited during the determined period of time.

15. The non-transitory compute

Assignees

• Qualcomm Inc

Inventors

• Alavoine Olivier
• Lee Sejoong
• Kazi Tauseef
• Booth Simon
• Regini Edoardo
• Jakushokas Renatas
• Patodia Saurabh
• Gemar Jeffrey
• Lo Haw-Jing
• Chamarty Vinod
• Andreev Boris
• Shen Tao
• Bhaskara Aravind
• Wang Wenbiao
• Molloy Stephen

Classifications

• G06F3/0673

  Single storage device · CPC title

• G06F1/3275 Primary

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F3/0625

  Power saving in storage systems · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title