Distributed mach-zehnder modulator (MZM) driver delay compensation

Patent metadata

Field	Value
Publication number	US-9964832-B2
Application number	US-201514723839-A
Country	US
Kind code	B2
Filing date	May 28, 2015
Priority date	May 28, 2015
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

An electronic driver circuit for use with a modulator such as a segmented Mach-Zehnder Modulator (MZM) is provided. The electronic driver circuit includes a first delay buffer implemented as a first complementary metal-oxide-semiconductor (CMOS) inverter and a second delay buffer implemented as a second CMOS inverter. The second CMOS inverter follows the first CMOS inverter and has a second gate width smaller than a first gate width of the first CMOS inverter. The first CMOS inverter is configured to produce a first delayed electrical signal from a received electrical signal and the second CMOS inverter is configured to produce a second delayed electrical signal from the first delayed electrical signal produced by the first CMOS inverter.

First claim

What is claimed is:

1. An electronic driver circuit for a segmented modulator, comprising:
a first delay stage comprising a first delay buffer and a first output buffer coupled to the first delay buffer, with the first delay buffer receiving an electrical signal input at a first delay stage input and outputting a first delayed electrical signal at a first delay stage output and to the first output buffer, with the first output buffer coupled to a first segment of the segmented modulator and with the first delay buffer comprising a first complementary metal-oxide-semiconductor (CMOS) inverter having a first gate width; and
a second delay stage including a second delay stage input coupled to and receiving the first delayed electrical signal from the first delay stage output, the second delay stage comprising a first metal trace coupled to a second delay buffer and a second output buffer coupled to the second delay buffer, with the second delay buffer outputting a second delayed electrical signal at a second delay stage output and to the second output buffer, wherein the second delayed electrical signal is generated from the first delayed electrical signal, with the second output buffer coupled to a second segment of the segmented modulator and with the second delay buffer comprising a second CMOS inverter having a second gate width that is smaller than the first gate width of the first CMOS inverter.

2. The electronic driver circuit of claim 1 , further comprising a third delay stage including a third delay stage input coupled to and receiving the second delayed electrical signal from the second delay stage output, the third delay stage comprising a second metal trace coupled to a third delay buffer, the third delay buffer outputting a third delayed electrical signal at a third delay stage output and to a third output buffer, wherein the third delayed electrical signal is generated from the second delayed electrical signal and wherein the third output buffer is coupled to a third segment of the segmented modulator, with the third output buffer comprising a third CMOS inverter having a third gate width that is smaller than the second gate width of the second CMOS inverter.

3. The electronic driver circuit of claim 2 , wherein the first output buffer comprises a fourth CMOS inverter having a fourth gate width, wherein the second output buffer comprises a fifth CMOS inverter having a fifth gate width, and wherein the third output buffer comprises a sixth CMOS inverter having a sixth gate width.

4. The electronic driver circuit of claim 3 , wherein the gate widths of the fourth CMOS inverter, the fifth CMOS inverter, and the sixth CMOS inverter are about the same and are independent of the gate widths of the first CMOS inverter, the second CMOS inverter, and the third CMOS inverter.

5. The electronic driver circuit of claim 2 , wherein the first gate width is about twice as wide as the second gate width and wherein the third gate width is about half as wide as the second gate width.

6. The electronic driver circuit of claim 2 , wherein the first gate width is about four times as wide as the second gate width and wherein the third gate width is about a quarter as wide as the second gate width.

7. The electronic driver circuit of claim 2 , wherein the first delayed electrical signal has been delayed by an active delay produced by the first delay buffer, wherein the second delayed electrical signal has been delayed by an active delay produced by the second delay buffer plus a passive delay produced by the first metal trace, and wherein the third delayed electrical signal has been delayed by an active delay produced by the third delay buffer plus a passive delay produced by the second metal trace.

8. The electronic driver circuit of claim 2 , wherein the delay in the third delayed electrical signal with respect to the received electrical signal comprises an active delay produced by the first delay buffer, an active delay produced by the second delay buffer, an active delay produced by the third delay buffer, a passive delay produced by the first metal trace, and a passive delay produced by the second metal trace.

9. The electronic driver circuit of claim 1 , wherein the first delayed electrical signal has been delayed by an active delay produced by the first delay buffer, and wherein the second delayed electrical signal has been delayed by an active delay produced by the second delay buffer and a passive delay produced by the first metal trace.

10. The electronic driver circuit of claim 9 , wherein the active delay produced by the first delay buffer is about 4 picoseconds (ps), wherein the active delay produced by the second delay buffer is about 4 ps, and wherein the passive delay produced by the first metal trace is about 4 ps.

11. An electronic driver circuit for a segmented modulator, comprising:
a first delay stage comprising a first active delay element having a first gate width, the first active delay element introducing a first active delay to a received electrical signal to produce a first delayed signal, the first delay stage being coupled to a first output buffer for driving a first segment of the segmented modulator; and
a second delay stage operably coupled to the first delay stage, the second delay stage comprising a first passive delay element and a second active delay element, the second active delay element having a second gate width smaller than the first gate width of the first active delay element, the first passive delay element introducing a first passive delay and the second active delay element introducing a second active delay to the first delayed signal to produce a second delayed signal, the second delay stage being coupled to a second output buffer for driving a second segment of the segmented modulator.

12. The electronic driver circuit of claim 11 , wherein a third delay stage is operably coupled to the second delay stage, the third delay stage comprising a second passive delay element and a third active delay element, the third active delay element having a third gate width smaller than the second gate width, the second passive delay element introducing a second passive delay and the third active delay element introducing a third active delay to the second delayed signal to produce a third delayed signal, the third delayed signal being coupled to a third output buffer for driving a third segment of the segmented modulator.

13. The electronic driver circuit of claim 12 , wherein each of the first active delay element, the second active delay element, and the third active delay element is a complementary metal-oxide-semiconductor (CMOS) inverter disposed in a delay buffer.

14. The electronic driver circuit of claim 12 , wherein each of the first output buffer, the second output buffer, and the third output buffer is a complementary metal-oxide-semiconductor (CMOS) inverter.

15. The electronic driver circuit of claim 11 , wherein the first passive delay element is a metal trace.

16. The electronic driver circuit of claim 15 , wherein a length of the metal trace is less than one-tenth of a wavelength of the received electrical signal.

17. A method of driving a circuit, comprising:
generating, at a first delay stage, a first delayed electrical signal from a received electrical signal using a first complementary metal-oxide-semiconductor (CMOS) inverter having a first gate width;
outputting the first delayed electrical signal to a first output buffer and a second delay stage;
driving, by the first output buffer, a first segment of a segmented modulator;
generating, at the sec

Assignees

• Futurewei Technologies Inc

Inventors

• Chen Morgan
• Gu Yifan
• Lee Hungyi
• Gu Liang
• Dang Yen
• Lei Gong
• Cao Yuming
• Shen Xiao
• Bai Yu Sheng

Classifications

• G02F1/2255 Primary

  controlled by a high-frequency electromagnetic component in an electric waveguide structure · CPC title

• G02F2001/212

  Physics · mapped topic

• G02F1/212

  Mach-Zehnder type · CPC title

• H03K5/134

  with field-effect transistors · CPC title