Method for cutting a carrier for electrical components

US9961777B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9961777-B2
Application numberUS-201214112233-A
CountryUS
Kind codeB2
Filing dateApr 17, 2012
Priority dateApr 20, 2011
Publication dateMay 1, 2018
Grant dateMay 1, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A trench ( 20 ) is introduced into a carrier ( 10 ) for electrical components ( 30 ) on a first surface (O 10 a ) of the carrier into the material of the carrier ( 10 ). The carrier ( 10 ) is cut through by a cut ( 60 ) being introduced into the material of the carrier from a second surface (O 10 b ) of the carrier ( 10 ), said second surface being situated opposite the first surface. The cut is implemented in such a way that the cut ( 60 ) runs through the trench ( 20 ) on the first surface (O 10 a ) of the carrier. By providing a trench ( 20 ) in the material layers of the carrier ( 10 ) which are near the surface, it is possible to prevent material from breaking out of the carrier during the singulation of devices ( 1, 2 ).

First claim

Opening claim text (preview).

What is claimed is: 1. A method for cutting a carrier for electrical components, comprising the steps of: providing a carrier for electrical components, wherein the electrical components are arranged on a first surface of the carrier and contact terminals are arranged on a second surface of the carrier, the second surface being situated opposite to the first surface; applying a film onto the second surface of the carrier such that the contact terminals penetrate into a material of the film; producing a trench in a material of the carrier on the first surface, wherein the carrier is fixed on the film while the trench is produced; arranging the film on the first surface of the carrier such that the film is applied onto a surface of the electrical components; and dicing the carrier for separating the electrical components by producing a cut in the material of the carrier from the second surface of the carrier while the film is arranged on the first surface of the carrier and onto the surface of the electrical components, wherein the cut is produced in such a way that it extends through the trench on the first surface of the carrier, and wherein the trench is produced in the material of the carrier with a width that is greater than the width of the cut. 2. The method according claim 1 , wherein the cut is produced in the material of the carrier with a cutting apparatus, wherein the cutting apparatus is placed onto the second surface of the carrier with a positioning accuracy which lies between +/−5 μm, and wherein the width of the trench corresponds to the width of the cutting apparatus plus the positioning accuracy with which the cutting apparatus is placed onto the second surface of the carrier. 3. The method according to claim 2 , wherein a saw blade is used as the cutting apparatus, and wherein the width of the saw blade of the cutting apparatus is chosen in such a way that the cut has a width between 10 μm and 50 μm. 4. The method according claim 3 , wherein the trench is produced in the material of the carrier with an additional cutting apparatus that features a saw blade, and wherein the width of the saw blade of the additional cutting apparatus is chosen in such a way that the trench is produced in the material of the carrier with a width between 15 μm and 80 μm. 5. The method according to claim 4 , wherein the width of the saw blade of the additional cutting apparatus is chosen in such a way that the trench is produced in the material of the carrier with a width of 40 μm. 6. The method according to claim 3 , wherein the cut has a width of 30 μm. 7. The method according to claim 1 , wherein the trench is produced in the material of the carrier with a depth in excess of 10 μm. 8. The method according to claim 7 , wherein the trench is produced in the material of the carrier with a depth in excess of 20 μm. 9. The method according to claim 1 , further comprising the step of: mounting the electrical components on the first surface of the carrier. 10. The method according to claim 1 , further comprising the step of: mounting contact terminals on the second surface of the carrier. 11. The method according to claim 1 , wherein the trench is produced in the material of the carrier by means of an etching method, or by means of a mechanical processing method. 12. The method according to claim 11 , wherein the trench is produced in the material of the carrier by means of dry etching, or by means of sawing. 13. The method according to claim 1 , wherein the carrier is realized in the form of a wafer. 14. The method according to claim 13 , wherein the carrier is realized in the form of a silicon material.

Assignees

Inventors

Classifications

  • batch processes · CPC title

  • of bump connectors · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

  • using batch processing · CPC title

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Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9961777B2 cover?
A trench ( 20 ) is introduced into a carrier ( 10 ) for electrical components ( 30 ) on a first surface (O 10 a ) of the carrier into the material of the carrier ( 10 ). The carrier ( 10 ) is cut through by a cut ( 60 ) being introduced into the material of the carrier from a second surface (O 10 b ) of the carrier ( 10 ), said second surface being situated opposite the first surface. The c…
Who is the assignee on this patent?
Stering Bernhard, Ams Ag
What technology area does this patent fall under?
Primary CPC classification H10W99/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).