Printed circuit boards by massive parallel assembly

Patent metadata

Field	Value
Publication number	US-9961771-B2
Application number	US-201213571252-A
Country	US
Kind code	B2
Filing date	Aug 9, 2012
Priority date	Mar 14, 2009
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

A method of forming an interconnect substrate includes providing at least two unit cells, arranging the unit cells to form a desired circuit pattern, and joining the unit cells to form the interconnect substrate having the desired circuit pattern.

First claim

What is claimed is:

1. A method of forming an interconnect substrate, comprising:
providing multiple unit cells in reservoirs to a sorting unit, wherein at least two unit cells have at least one conductive line on a face of the unit cell and the at least two unit cells are of a material bondable to others of the multiple unit cells;
sorting and orienting the multiple unit cells, using the sorting unit, according to a desired circuit pattern to produce multiple sorted and oriented unit cells;
transferring the multiple oriented and sorted unit cells from the sorting unit to an image transfer unit;
dispensing and arranging the multiple unit cells from the image transfer unit to form the desired circuit pattern such that a conductive line on a face of a first of the at least two unit cells contacts a conductive line on a face of a second unit cell of the at least two unit cells to form part of the desired circuit pattern; and
joining the multiple unit cells to form the interconnect substrate having the desired circuit pattern.

2. The method of claim 1 , wherein at least one additional unit cell of the multiple cells is only an insulator, the insulator requiring placement without arranging.

3. The method of claim 1 , wherein at least one of the at least two unit cells is an insulator with a conductive line on one side of the insulator.

4. The method of claim 1 , wherein at least one of the at least two unit cells is an insulator with a conductive line on both sides of the insulator.

5. The method of claim 1 , wherein at least one of the at least two unit cells is an insulator with conductive lines on both sides of the insulator, and at least one via to electrically connect the lines together.

6. The method of claim 1 , wherein arranging the multiple unit cells comprises one of manipulating electrical fields, manipulating magnetic fields, manipulating surface energies, using digitally addressed heaters, digitally addressed solder melting, laser-addressed pick-and-place, and micro-pick-and-place with adhesive.

7. The method of claim 1 , wherein joining the multiple unit cells comprises one of fusing, sintering, plating, self-assembly of conductive lines, shrinking a substrate upon which the at least two unit cells reside, expanding the at least two unit cells and printing conductive lines to connect the at least two unit cells.

8. The method of claim 1 , wherein the multiple unit cells are at least partially made up of a plastic and joining the multiple unit cells comprises cross-linking the plastic.

9. The method of claim 1 , wherein providing the multiple unit cells comprises dispensing the unit cells using a print engine.

10. The method of claim 1 , wherein dispensing the multiple unit cells comprises one of dispensing them from a solution or dispensing them as dry particles.

11. The method of claim 1 , wherein providing the multiple unit cells comprises manufacturing the unit cells.

12. The method of claim 1 , wherein providing the multiple unit cells comprises acquiring unit cells that have been manufactured.

Assignees

• Lu Jengping
• Chow Eugene M
• Palo Alto Res Ct Inc

Inventors

• Lu Jengping
• Chow Eugene M

Classifications

• H05K2201/09963

  Programming circuit by using small elements, e.g. small PCBs · CPC title

• H05K1/14

  Structural association of two or more printed circuits (providing electric connection to or between printed circuits H05K1/11, H01R12/00) · CPC title

• H05K1/142 Primary

  Arrangements of planar printed circuit boards in the same plane, e.g. auxiliary printed circuit insert mounted in a main printed circuit · CPC title

• Y10T29/49155

  Manufacturing circuit on or in base · CPC title

• H05K1/0286

  Programmable, customizable or modifiable circuits (by programmable non-printed jumper connections H05K3/222) · CPC title