Instruction for Performing SIMD affine transformation

Patent metadata

Field	Value
Publication number	US-9960907-B2
Application number	US-201414316624-A
Country	US
Kind code	B2
Filing date	Jun 26, 2014
Priority date	Dec 28, 2007
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

Instructions and logic provide general purpose GF(2 8 ) SIMD cryptographic arithmetic functionality. Embodiments include a processor to decode an instruction for a SIMD affine transformation specifying a source data operand, a transformation matrix operand, and a translation vector. The transformation matrix is applied to each element of the source data operand, and the translation vector is applied to each of the transformed elements. A result of the instruction is stored in a SIMD destination register. Some embodiments also decode an instruction for a SIMD binary finite field multiplicative inverse to compute an inverse in a binary finite field modulo an irreducible polynomial for each element of the source data operand. Some embodiments also decode an instruction for a SIMD binary finite field multiplication specifying first and second source data operands to multiply each corresponding pair of elements of the first and second source data operand modulo an irreducible polynomial.

First claim

What is claimed is:

1. A processor comprising:
a decode stage to decode a first instruction for a Single Instruction Multiple Data (SIMD) affine transformation, the first instruction specifying a source data operand set, a transformation matrix operand, and a translation vector operand; and
one or more execution units, responsive to the decoded first instruction, to:
perform a SIMD affine transformation by applying the transformation matrix operand to each element of the source data operand set, and applying the translation vector operand to each transformed element of the source data operand set; and
store a result of the first instruction in a SIMD destination register.

2. The processor of claim 1 , wherein said one or more execution units, responsive to the decoded first instruction, are further to compute a SIMD binary finite-field multiplicative inverse modulo a specific irreducible polynomial for each affine transformed element of the source data operand set.

3. The processor of claim 2 , wherein the specific irreducible polynomial is specified in an immediate operand of the first instruction as a hexadecimal control value 1B to indicate x8+x4+x3+x+1 in the Galois field GF(28).

4. The processor of claim 1 , wherein the first instruction specifies said SIMD destination register as a destination operand.

5. The processor of claim 1 , wherein the first instruction specifies a SIMD register to hold 16 byte elements as the source data operand set.

6. The processor of claim 1 , wherein the first instruction specifies a SIMD register to hold 32 byte elements as the source data operand set.

7. The processor of claim 1 , wherein the first instruction specifies a SIMD register to hold 64 byte elements as the source data operand set.

8. The processor of claim 1 , wherein the first instruction specifies a SIMD register to hold at least 64 1-bit elements as the transformation matrix operand.

9. The processor of claim 1 , wherein the first instruction specifies said translation vector operand as an 8-bit vector in an immediate operand.

10. The processor of claim 1 , wherein applying the transformation matrix operand to each element of the source data operand set is performed as matrix multiplications in the Galois field GF(28).

11. The processor of claim 1 , wherein applying the translation vector operand to each transformed element of the source data operand set is performed as vector additions in the Galois field GF(28).

12. A non-transitory machine-readable medium to record functional descriptive material comprising one or more executable instructions that, when executed by a processor on behalf of a thread of a machine, cause the processor to:
access, by the processor, a source data operand set of elements, a transformation matrix operand, and a translation vector operand;
perform a Single Instruction Multiple Data (SIMD) affine transformation by applying the transformation matrix operand to each element of the source data operand set, and applying the translation vector operand to each transformed element of the source data operand set; and
store a result of the SIMD affine transformation in a SIMD destination register.

13. The non-transitory machine-readable medium of claim 12 , including one or more executable instructions, which if executed on behalf of a thread of a machine further causes the machine to compute a SIMD binary finite-field multiplicative inverse modulo a specific irreducible polynomial for each affine transformed element of the source data operand set.

14. The non-transitory machine-readable medium of claim 12 , wherein applying the transformation matrix operand to each element of the source data operand set is performed as matrix multiplications in the Galois field GF(28).

15. The non-transitory machine-readable medium of claim 12 , wherein applying the translation vector operand to each transformed element of the source data operand set is performed as vector additions in the Galois field GF(28).

16. A method comprising:
decoding, by a processor, a first instruction for a Single Instruction Multiple Data (SIMD) affine transformation, the first instruction specifying a source data operand set, a transformation matrix operand, and a translation vector operand;
performing, by the processor, a SIMD affine transformation responsive to the decoded first instruction by applying the transformation matrix operand to each element of the source data operand set, and applying the translation vector operand to each transformed element of the source data operand set; and
storing a result of the first instruction in a SIMD destination register.

17. The method of claim 16 further comprising computing a SIMD binary finite-field multiplicative inverse modulo a specific irreducible polynomial for each affine transformed element of the source data operand set.

18. The method of claim 16 , wherein applying the transformation matrix operand to each element of the source data operand set is performed as matrix multiplications in the Galois field GF(28).

19. The method of claim 16 , wherein applying the translation vector operand to each transformed element of the source data operand set is performed as vector additions in the Galois field GF(28).

20. A processing system comprising:
a memory to store a first instruction for a SIMD secure hashing algorithm round slice; and
a processor comprising:
an instruction fetch stage to fetch the first instruction;
a decode stage to decode a first instruction for a Single Instruction Multiple Data (SIMD) affine transformation, the first instruction specifying a source data operand set, a transformation matrix operand, and a translation vector operand; and
one or more execution units, responsive to the decoded first instruction, to:
perform a SIMD affine transformation by applying the transformation matrix operand to each element of the source data operand set, and applying the translation vector operand to each transformed element of the source data operand set; and
store a result of the first instruction in a SIMD destination register.

21. The processing system of claim 20 , wherein said one or more execution units, responsive to the decoded first instruction, are further to compute a SIMD binary finite-field multiplicative inverse modulo a specific irreducible polynomial for each affine transformed element of the source data operand set.

22. The processing system of claim 20 , wherein said decode stage is to decode a second instruction for a SIMD binary finite field multiplicative inverse to generate a first micro-instruction and a second micro-instruction, the second instruction specifying a second source data operand set, and a monic irreducible polynomial; and
said one or more execution units, responsive to the decoded second instruction, to:
compute a binary finite-field multiplicative inverse element for each element of the source data operand set according to the first micro-instruction;
reduce the binary finite-field multiplicative inverse element of each element of the source data operand set modulo the irreducible polynomial according to the second micro-instruction; and
store a result of the second instruction in a second SIMD destination register.

23. The processing system of claim 22 , wherein the irreducible polynomial is specified in the second instruction mnemonic as 1B to indicate x8+x4+x3+x +1 in the Galois field GF(28).

24. The processing system of claim 20 , w

Assignees

• Intel Corp

Inventors

• Gueron Shay

Classifications

• G06F7/00 Primary

  Methods or arrangements for processing data by operating upon the order or content of the data handled (logic circuits H03K19/00) · CPC title

• H04L9/0631 Primary

  Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms · CPC title

• G06F9/30196

  using decoder, e.g. decoder per instruction set, adaptable or programmable decoders · CPC title

• G06F9/30149

  of variable length instructions · CPC title

• G06F9/30007

  to perform operations on data operands · CPC title