System and method for a differential pulse position modulation encoder and decoder

Patent metadata

Field	Value
Publication number	US-9960853-B2
Application number	US-201615284680-A
Country	US
Kind code	B2
Filing date	Oct 4, 2016
Priority date	Oct 4, 2016
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

A system and method using Differential Pulse Position Modulation (DPPM) to encode digital data so that it can be transmitted using an infrared (IR) link. The digital data is then decoded upon receipt. This invention can be implemented in software and run on an FPGA (or the like) for prototyping and integration with existing designs. The encoding, decoding and sensitive timing are handled by dedicated hardware, which greatly increases the speed of these processes because it frees up the processor to accomplish other tasks.

First claim

What is claimed is:

1. A method of encoding digital data comprising:
receiving a first digital signal data from a source;
storing the first digital signal data in a first latch;
sending an instruction to the source that it is clear to send a second digital signal data;
storing the first digital signal data in a first counter;
activating a first delay timer trigger for a first delay timer and a, decrement timer trigger for a decrement timer simultaneously with storing the first digital signal data to the first counter;
sending a signal to output a Differential Pulse Position Modulation (DPPM) pulse simultaneously with storing the first digital signal data to the first counter;
connecting the decrement timer to the first counter;
decrementing the first digital signal data stored in the first counter by one on each rising edge of a decrement timer pulse;
checking the first counter to determine whether the first digital signal data is zero at each falling edge of the decrement time pulse;
sending a signal to output a DPPM pulse when the first digital signal data is decremented to zero; and
receiving a second digital signal data; and,
repeating the above steps, except for sending a signal to output a DPPM pulse simultaneously with storing the first digital signal data to the counter, until the source sends an instruction that there is no more data to be transmitted.

2. The method of claim 1 , wherein the delay timer and the decrement timer are connected so that the decrement timer does not begin until the delay timer is complete to create a minimum delay time between adjacent signal pulses to guarantee the source to cycle in or out new data.

3. The method of claim 2 , wherein the minimum delay time depends on what additional task are assigned to the source.

4. The method of claim 3 , wherein sending a signal to output the first digital signal data when the first digital signal data is decremented to zero is delayed.

5. The method of claim 1 , wherein the method is implemented using discrete components, using an integrated circuit designed for that purpose, using a Hardware Description Language (HDL) on a Complex Programmable Logic Device (CPLD), Field-Programmable Gate Array (FPGA).

6. The method of claim 1 , where components are synchronized within a transmitter using a clock signal, such that the clock need not be transmitted with the data to allow it to be decoded.

7. The method of claim 1 , where an additional parity bit or other error correction scheme is added to allow for error detection or error correction.

8. A method of decoding the DPPM data described above, comprising:
receiving an input signal that was encoded by the method of claim 1 ;
detecting each DPPM pulse;
clearing a second counter simultaneously with detecting the first DPPM pulse;
activating a second delay timer trigger for a second delay timer and an increment timer trigger for an increment timer simultaneously with detecting each DPPM pulse;
connecting the increment timer to the second counter;
incrementing the second counter by one on each rising edge of an increment timer pulse;
storing the current counter value in the second counter simultaneously with detecting the next DPPM pulse,
clearing the current counter value once it has been successfully stored in the second counter;
sending a signal to a controller that data is ready to be read; and,
repeating the above steps until no more DPPM pulses are received.

Assignees

• Collins Daniel
• Shevach Glenn
• Blair Mark
• Us Navy

Inventors

• Collins Daniel
• Shevach Glenn
• Blair Mark

Classifications

• H04B10/60

  Receivers · CPC title

• H04B10/524 Primary

  Pulse modulation · CPC title

• H04B10/11 Primary

  Arrangements specific to free-space transmission, i.e. transmission through air or vacuum · CPC title