Integrated circuit device with programmable analog subsystem

Patent metadata

Field	Value
Publication number	US-9960773-B2
Application number	US-201615269479-A
Country	US
Kind code	B2
Filing date	Sep 19, 2016
Priority date	Nov 25, 2014
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, a plurality of reconfigurable analog circuit blocks, at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; and a digital section comprising digital circuits; wherein each analog block includes dedicated of signal lines coupled to the at least one analog routing block.

First claim

What is claimed is:

1. An integrated circuit (IC) device, comprising:
an analog block comprising:
a fixed function analog circuit; and
a reconfigurable analog circuit block;

an analog routing block reconfigurable to provide signal paths between the analog block, wherein:
the analog block comprises a dedicated signal line coupled to the analog routing block, wherein the dedicated line is dedicated to only sending data between the analog block and the analog routing block; and
the reconfigurable analog circuit block comprises a direct signal line coupling the reconfigurable analog circuit block to an external connection of the IC device without passing through any switch.

2. The IC device of claim 1 , wherein the analog block comprises a programmable reference block (PRB) configured to generate a plurality of reference values.

3. The IC device of claim 2 , wherein the PRB has a direct connection for each of a plurality of reference values to a second analog block.

4. The IC device of claim 1 , further wherein the reconfigurable analog circuit block is configurable, at least in part, in response to a corresponding digital control signal, and wherein the IC device further comprises:
a digital control section configured to generate the digital control signal.

5. The IC device of claim 4 , further comprising:
a processor circuit; and
the digital control section to generate the digital control signal in response to output data from the processor circuit.

6. The IC device of claim 1 , wherein the reconfigurable analog circuit block comprises:
a continuous time (CT) block comprising a reconfigurable amplifier circuit; and
a discrete time block comprising an amplifier with a reconfigurable switch network having switches commonly controlled by a clock input.

7. An integrated circuit (IC) device, comprising:
a reconfigurable analog routing signal fabric comprising a plurality of shielded signal lines;
a analog block comprising:
a fixed function analog circuit with a dedicated signal line connected to the analog routing signal fabric,
a reconfigurable analog circuit block comprising:
a dedicated signal line connected to the analog routing signal fabric, wherein the dedicated signal line is dedicated to only sending data between the reconfigurable analog circuit block and the analog routing signal fabric; and
a direct signal line coupling the reconfigurable analog circuit block to an external connection of the IC device without passing through any switch.

8. The IC device of claim 7 , wherein the plurality of shielded signal lines comprises:
first signal lines formed from a first conductive layer; and
second signals lines formed from the first conductive layer and formed between the first signal lines, wherein the second signals lines are electrically coupled to one another.

9. The IC device of claim 8 , wherein the shielded signal lines further comprise a second conductive layer at a different vertical layer than the first conductive layer, wherein the second conductive layer is formed over the first signal lines and the second signal lines and wherein the second conductive layer is electrically coupled to the shielding signal lines.

10. The IC device of claim 7 , wherein the fixed function analog circuit comprises an analog-to-digital converter (ADC) circuit.

11. The IC device of claim 7 , wherein the reconfigurable analog circuit block comprises:
a continuous time (CT) block comprising a reconfigurable amplifier circuit, and
a discrete time block comprising an amplifier with a reconfigurable switch network including switches commonly controlled by a clock input.

12. The IC device of claim 7 , further comprising a digital section comprising digital circuit operatively coupled with the analog block.

13. A method, comprising:
in response to a digital configuration signal, interconnecting a analog block using a reconfigurable analog signal routing fabric, wherein:
the analog block comprising:
a fixed function analog circuit with a dedicated signal line connected to the analog signal routing fabric, wherein the dedicated signal line is dedicated to only sending data between the analog block and the analog signal routing fabric, and
a first reconfigurable analog circuit block with a dedicated signal line connected to the analog signal routing fabric, wherein the first reconfigurable analog circuit block includes a direct signal line coupling the first reconfigurable analog circuit block to an external connection of an integrated circuit (IC) device without passing through any switch, and wherein the first reconfigurable analog circuit block is a continuous time block (CTB) comprising a reconfigurable amplifier circuits; and

performing continuous time signal processing in the CTB block.

14. The method of claim 13 , further comprising generating the digital configuration signal with a digital section comprising a digital circuit.

15. The method of claim 13 , wherein the analog block further comprises a second reconfigurable analog circuit block, wherein the second reconfigurable analog circuit block comprises a discrete time block having an amplifier with a reconfigurable switch network that includes a group of switches commonly controlled by a clock input.

16. The method of claim 15 , further comprising performing discrete time signal processing in the discrete time block.

17. The method of claim 13 , further comprising generating the digital configuration signal in response to an instruction from a processor circuit.

18. The method of claim 13 , further comprising generating the digital configuration signal in response to an instruction from a reconfigurable digital circuit.

19. The method of claim 13 , wherein the reconfigurable analog block comprises a programmable reference block (PRB) configured to generate a programmable reference value.

20. The method of claim 19 , further comprising providing the programmable reference value directly to the analog block from the programmable reference block.

Assignees

• Cypress Semiconductor Corp

Inventors

• Thiagarajan Eashwar
• Kutz Harold M
• Klein Hans
• Johal Jaskarn Singh
• Vanitegem Jean-Paul
• Castor-Perry Kendall V
• Hastings Mark
• Richardson Jr Amsby D
• Pai Maroor Anasuya
• Khan Ata
• Seguine Dennis R
• Liepold Carl Ferdinand
• Ozbek Onur

Classifications

• H03K19/17732

  Macroblocks · CPC title

• H03K19/17736 Primary

  Structural details of routing resources · CPC title

• H03K19/17712

  one of the matrices at least being reprogrammable · CPC title