Isolator with reduced susceptibility to parasitic coupling

Patent metadata

Field	Value
Publication number	US-9960671-B2
Application number	US-201414588112-A
Country	US
Kind code	B2
Filing date	Dec 31, 2014
Priority date	Dec 31, 2014
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

A capacitive isolation system, capacitive isolator, and method of operating the same are disclosed. The capacitive isolation system is described to include a first semiconductor die and a second semiconductor die each having capacitive elements established thereon and positioned in a face-to-face configuration. An isolation layer is provided between the first and second semiconductor die so as to establish an isolation boundary therebetween. Capacitive coupling is used to carry information across the isolation boundary.

First claim

What is claimed is:

1. An isolator, comprising:
a first semiconductor die comprising a first surface comprising a plurality of pads established thereon, wherein the plurality of pads established on the first surface of the first semiconductor die include:
a first capacitive element; and
a first bonding pad that facilitates wirebonding and enables an electrical connection between a first external circuit and the first capacitive element of the first semiconductor die;

a second semiconductor die comprising a first surface facing the first surface of the first semiconductor die, wherein the first surface of the second semiconductor die comprises a plurality of pads established thereon, wherein the plurality of pads established on the first surface of the second semiconductor die include:
a second capacitive element, wherein the first semiconductor die and second semiconductor die are positioned relative to one another such that the first capacitive element and second capacitive element oppose one another and at least partially overlap one another to form a capacitor; and
a second bonding pad that facilitates wirebonding and enables an electrical connection between a second external circuit and the second capacitive element of the second semiconductor die; and

an isolation layer positioned between the first surface of the first semiconductor die and the first surface of the second semiconductor die so as to provide an electrical isolation boundary between the first external circuit and the second external circuit, wherein the isolation layer comprises at least one opening that exposes the first bonding pad and/or second bonding pad for wirebonding.

2. The isolator of claim 1 , wherein the first capacitive element comprises a metal plate covered by a passivation layer.

3. The isolator of claim 2 , wherein the first capacitive element and second capacitive element are both in physical contact with the isolation layer.

4. The isolator of claim 1 , wherein the first capacitive element corresponds to a first receiving capacitive element, wherein the second capacitive element corresponds to a first transmitting capacitive element, and wherein an area of the first receiving capacitive element is smaller than an area of the first transmitting capacitive element.

5. The isolator of claim 4 , wherein a first isolation capacitor is formed between the first receiving capacitive element and the first transmitting capacitive element and wherein the first isolation capacitor carries information from a drive signal across the electrical isolation boundary without directly flowing current across the electrical isolation boundary.

6. The isolator of claim 4 , wherein the first semiconductor die further comprises a third capacitive element, wherein the second semiconductor die further comprises a fourth capacitive element, wherein the third and fourth capacitive elements oppose one another and at least partially overlap one another to form a second isolation capacitor.

7. The isolator of claim 6 , wherein the third capacitive element corresponds to a second transmitting capacitive element, wherein the fourth capacitive element corresponds to a second receiving capacitive element, and wherein the second isolation capacitor is formed between the second receiving capacitive element and the second transmitting capacitive element and wherein the second isolation capacitor carries information from a drive signal across the electrical isolation boundary without directly flowing current across the electrical isolation boundary.

8. The isolator of claim 7 , wherein the first transmitting capacitive element and the second transmitting capacitive element are arranged in a common centroid configuration.

9. The isolator of claim 1 , wherein the first semiconductor die comprises first driver circuitry positioned between the first surface of the first semiconductor die and a second surface of the first semiconductor die, wherein the first driver circuitry carries electrical current from the first bonding pad to the first capacitive element.

10. The isolator of claim 9 , wherein the first driver circuitry is positioned in at least a partial overlapping arrangement with respect to the first capacitive element.

11. The isolator of claim 1 , wherein the isolation layer comprises a polyimide tape having adhesive on both sides thereof and wherein the isolation layer covers the first and second capacitive elements and exposes the first and second bonding pads.

12. The isolator of claim 1 , wherein the isolation layer comprises a polyimide film formed on the first surface of the first semiconductor die as well as the first surface of the second semiconductor die.

13. The isolator of claim 1 , wherein the first capacitive element comprises a main receiving portion and a secondary receiving portion, the main receiving portion including a first pad area, the secondary receiving portion including a plurality of second pad areas that are smaller than the first pad area, wherein the main receiving portion and the secondary receiving portion both overlap the second capacitive element.

14. The isolator of claim 13 , wherein the plurality of second pad areas of the secondary receiving portion are selectively switchable on and off so as to enable adjustment of an effective size of the first capacitive element, thereby enabling adjustment of a capacitance between the first capacitive element and the second capacitive element.

15. The isolator of claim 14 , further comprising a peak differential detector configured to compare a first peak amplitude measured between a first isolation capacitor established between the first semiconductor die and the second semiconductor die with a second peak amplitude measured between a second isolation capacitor established between the first semiconductor die and the second semiconductor die and based on such a comparison selectively switch on or off the second pad areas of the secondary receiving portion.

16. The isolator of claim 15 , wherein the peak differential detector selectively switches on or off the second pad areas in an effort to equalize the first isolation capacitor with the second isolation capacitor.

17. The isolator of claim 13 , wherein the plurality of second pad areas include a first pad of a first size and a second pad of a second size that is different from the first size.

18. An isolation system, comprising:
a first lead frame configured for connection to a first external circuit, the first lead frame having a bonding surface and a top surface of a lead that are separated by a first downset distance formed by folding the first lead frame, wherein a first die is mounted on the bonding surface of the first lead frame;
a second lead frame configured for connection to a second external circuit, the second lead frame having a bonding surface and a top surface of a lead that are separated by a second downset distance formed by folding the second lead frame, wherein a second die is mounted on the bonding surface of the second lead frame, wherein the first die and second die each have one or more capacitive elements established thereon, wherein the bonding surface of the first lead frame and the bonding surface of the second lead frame at least partially overlap and face one another, and wherein the first die and second die are positioned in a face-to-face configuration thereby creating one or more isolation capacitors between the first die and second die with overlapping capacitive elements; and
an isolation layer positioned between the first die and the second die so as

Assignees

• Avago Technologies General Ip

Inventors

• Ho Dominique
• Chang Kwee Chong
• Lee Kah Weng
• Misek Brian J

Classifications

• H10W90/293

  characterised by non-galvanic coupling between the chips, e.g. capacitive coupling · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W72/865

  Die-attach connectors and bond wires · CPC title

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

• H10W72/859

  Bump connectors and bond wires · CPC title