Termination structure with multiple embedded potential spreading capacitive structures for trench MOSFET

Patent metadata

Field	Value
Publication number	US-9960237-B2
Application number	US-201514684570-A
Country	US
Kind code	B2
Filing date	Apr 13, 2015
Priority date	Feb 12, 2010
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.

First claim

We claim:

1. A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) for terminating an active area semiconductor device being located along the top surface of a bulk semiconductor layer (BSL) of a first conductivity type having a proximal bulk semiconductor wall (PBSW) separating the TSMEC from the active area semiconductor device, the TSMEC comprises an oxide-filled large deep trench (OFLDT) being bounded by the PBSW and a distal bulk semiconductor wall (DBSW) wherein the OFEDT further comprises:
an oxide trench of trench size (TCS) and trench depth (TCD) into the BSL wherein TCS extends from the PBSW to the DBSW; and
a plurality of embedded capacitive structures (EBCS) each formed of a conductive embedded polycrystalline semiconductor region (EPSR) surrounded by an oxide column (OXC) located inside the oxide trench, the plurality of EBCS sequentially placed between the PBSW and the DBSW and completely filling an entire space between the PBSW and the DBSW wherein the oxide extends an entire space between adjacent EPSR; wherein a proximal EPSR located next to the PBSW is electrically connected to a doped region of a second conductivity type opposite the first conductivity type disposed on a top portion of the PBSW.

2. The TSMEC of claim 1 wherein a distal EPSR located next to the DBSW is electrically connected to a termination region metal disposed over the DBSW.

3. The TSMEC of claim 2 wherein the termination region metal being electrically connected to a drain potential.

4. The TSMEC of claim 2 wherein the DBSW further comprises a doped region of the second conductivity type disposed on a top portion of the DBSW.

5. The TSMEC of claim 1 wherein the proximal EPSR located next to the PBSW is electrically connected to a top electrode.

6. A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) for terminating an active area semiconductor device being located along the top surface of a bulk semiconductor layer (BSL) of a first conductivity type having a proximal bulk semiconductor wall (PBSW) separating the TSMEC from the active area semiconductor device, the TSMEC comprises an oxide-filled large deep trench (OFLDT) being bounded by the PBSW and a distal bulk semiconductor wall (DBSW),
wherein the OFLDT further comprises:
an oxide trench of trench size (TCS) and trench depth (TCD) into the BSL; and
a plurality of embedded capacitive structures (EBCS) each formed of a conductive embedded polycrystalline semiconductor region (EPSR) surrounded by an oxide located inside the oxide trench, the plurality of EBCS sequentially placed between the PBSW and the DBSW and completely filling an entire space between the PBSW and the DBSW; wherein a proximal EPSR located next to the PBSW is electrically connected to a top electrode and is electrically connected to a doped region of a second conductivity type opposite the first conductivity type disposed on a top portion of the PBSW; and

wherein the DBSW further comprises:
a doped region of the second conductivity type disposed on a top portion of the DBSW.

7. The TSMEC of claim 1 wherein a distal EPSR located next to the DBSW is electrically connected to a termination region metal disposed over the DBSW.

8. The TSMEC of claim 2 wherein the termination region metal being electrically connected to a drain potential.

Assignees

• Alpha & Omega Semiconductor

Inventors

• Wang Xiaobin
• Bhalla Anup
• Yilmaz Hamza
• Ng Daniel

Classifications

• H10W10/0121

  in regions recessed from the surface, e.g. in trenches or grooves · CPC title

• H10W10/13

  formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI] · CPC title

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H01L29/0696

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic