Temperature-based memory access

Patent metadata

Field	Value
Publication number	US-9959936-B1
Application number	US-201514643751-A
Country	US
Kind code	B1
Filing date	Mar 10, 2015
Priority date	Mar 12, 2014
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

The present disclosure describes apparatuses and techniques that enable temperature-based memory access. In some aspects, a request to access a memory device is received. In response to the request, respective temperatures are determined for multiple locations of the memory device. Based on these respective temperatures, a selection can be made of which of the multiple locations to access. Alternately or additionally, an order in which to access the multiple locations can be determined based on the respective temperatures. The location(s) of the memory device are then accessed based on the selection or the determined order effective to minimize an increase in the memory device's temperature.

First claim

What is claimed is:

1. A method comprising:
receiving a request to access a memory device, a type of the request being one of (i) a read request, (ii) a write request, or (iii) an erase request;
determining the type of the request to access the memory device as one of (i) the read request, (ii) the write request, or (iii) the erase request;
accessing, in response to the request, a map of temperature values for locations of the memory device to determine respective temperature values of a first location and a second location of the memory device;
selecting, based on the respective temperature values of the first and second locations, which of the two locations to access;
accessing the selected location of the memory device to complete the request;
increasing, based on the type of the request to access the memory device, a temperature value of the map associated with the selected location to reflect heat generated by the access of the memory device, the temperature value of the map increased by a respective predefined heat increment associated with (i) the read request, (ii) the write request, or (iii) the erase request, at least two of the respective predefined heat increments being different; and
applying a filter to the map of temperature values effective to estimate dissipation of heat from at least the selected location to other locations of the memory device.

2. The method as recited in claim 1 , wherein selecting one of the two locations based on the respective temperatures is effective to minimize an increase in the memory device's temperature.

3. The method as recited in claim 1 , wherein the first and second locations of the memory device are free locations and the method further comprises determining, from multiple locations of the memory device, that the first and second locations of the memory device are free.

4. The method as recited in claim 1 , wherein the request is made via a logical address of the memory device and the method further comprises mapping the logical address of the request to the selected location of the memory device to enable completion of the request.

5. The method as recited in claim 1 , wherein the memory device comprises a three-dimensional (3D) memory device or a two-dimensional (2D) memory device.

6. The method as recited in claim 1 , wherein the filter applied to the map of temperature values is configured based on an optical function that is useful to predict or estimate dissipation of the heat between physical locations of the memory device.

7. The method as recited in claim 1 wherein the predefined heat increment associated with the read request is less than the predefined heat increment associated with the write request.

8. A System-on-Chip comprising:
a memory interface through which locations of a memory device are accessible;
a host interface configured to receive, from a host device, requests to access the memory device;
computer-readable media configured to maintain a temperature map of respective temperature information for the memory device's locations;
a memory access manager to implement operations comprising:
receiving, via the host interface, a request to access the memory device, a type of the request being one of (i) a read request, (ii) a write request, or (iii) an erase request;
determining the type of the request to access the memory device as one of (i) the read request, (ii) the write request, or (iii) the erase request;
determining, by accessing the temperature map, respective temperatures of at least two of the memory device's locations;
selecting, based on the respective temperatures of the at least two locations, one of the at least two locations;
accessing, via the memory interface, the selected location of the memory device to complete the request of the host device;
increasing, based on the type of the request to access the memory device, a temperature value of the map associated with the selected location to reflect heat generated by the access of the memory device, the temperature value of the map increased by a respective predefined heat increment associated with (i) the read request, (ii) the write request, or (iii) the erase request, at least two of the respective predefined heat increments being different; and
applying a filter to the temperature map effective to estimate dissipation of heat from at least the selected location to other locations of the memory device.

9. The System-on-Chip as recited in claim 8 , wherein the computer-readable media is further configured to maintain a map of respective occupation information for the memory device's locations and the operations implemented by the memory access controller further comprise determining which of the memory device's locations are available for access.

10. The System-on-Chip as recited in claim 8 , wherein selecting one of the at least two locations based on the respective temperatures is effective to minimize an increase in the memory device's temperature.

11. The System-on-Chip as recited in claim 8 , wherein the filter applied to the map of temperature values is configured based on an optical function that comprises one of a blurring function, Gaussian function, smoothing function, or saturation function.

12. The System-on-Chip as recited in claim 8 , wherein the memory device comprises a three-dimensional (3D) memory device or a two-dimensional (2D) memory device.

13. The System-on-Chip as recited in claim 8 , wherein the predefined heat increment associated with the read request is less than the predefined heat increment associated with the write request or the predefined heat increment associated with the erase operation.

14. One or more computer-readable memory devices storing processor-executable instructions that, responsive to execution by a hardware-based processor, implement a memory access manager to perform operations comprising:
receiving a request to access a memory device, a type of the request being one of (i) a read request, (ii) a write request, or (iii) an erase request;
determining the type of the request to access the memory device as one of (i) the read request, (ii) the write request, or (iii) the erase request;
accessing, in response to the request, a map of temperature values for locations of the memory device to determine respective temperatures of a first location and a second location of the memory device;
selecting, based on the respective temperatures of the first and second locations, which of the two locations to access;
accessing the selected location of the memory device to complete the request;
increasing, based on the type of the request to access the memory device, a temperature value of the map associated with the selected location to reflect heat generated by the access of the memory device, the temperature value of the map increased by a respective predefined heat increment associated with (i) the read request, (ii) the write request, or (iii) the erase request, at least two of the respective predefined heat increments being different; and
applying a filter to the map of temperature values effective to estimate dissipation of heat from at least the selected location to other locations of the memory device.

15. The one or more computer-readable memory devices as recited in claim 14 , wherein selecting one of the two locations based on the respective temperatures is effective to minimize an increase in the memory device's temperature.

16. The one or more computer-readable memory devices as recited in claim 14 , wherein the first and second locations of the memory device are free locations and the memory

Assignees

• Marvell Int Ltd

Inventors

• Song Jong-Uk

Classifications

• G11C29/12005 Primary

  comprising voltage or current generators · CPC title

• G06F12/023 Primary

  Free address space management · CPC title

• G06F2212/1044

  Space efficiency improvement · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F2212/7204

  Capacity control, e.g. partitioning, end-of-life degradation · CPC title