Semiconductor device and module adapted to both MIPI C-PHY and MIPI D-PHY

Patent metadata

Field	Value
Publication number	US-9959805-B2
Application number	US-201615218167-A
Country	US
Kind code	B2
Filing date	Jul 25, 2016
Priority date	Jul 27, 2015
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

A semiconductor device includes first to sixth external connection terminals, a first receiver connected to the first and second external connection terminals, a second receiver connected to the third and fourth external connection terminals, a third receiver connected to the fifth and sixth external connection terminals, a C-PHY block, a D-PHY block and a main processing section. The C-PHY block is configured to generate first reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI C-PHY specification. The D-PHY block is configured to generate second reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI D-PHY specification. The main processing section is configured to selectively receive the first and second reception data and perform desired processing on the received data.

First claim

What is claimed is:

1. A semiconductor device module, comprising:
first to sixth external connection terminals;
a first receiver connected to the first and second external connection terminals;
a second receiver connected to the third and fourth external connection terminals;
a third receiver connected to the fifth and sixth external connection terminals;
a C-PHY block configured to generate first reception data by performing signal processing on signals received from the first to third receivers in accordance with the Mobile Industry Processor Interface (MIPI) C-PHY specification;
a D-PHY block configured to generate second reception data by performing signal processing on signals received from the first to third receivers in accordance with the MIPI D-PHY specification; and
a main processing section configured to selectively receive the first and second reception data and perform desired processing on the received data.

2. The semiconductor device module according to claim 1 , wherein the C-PHY block comprises:
a clock recovery circuit configured to generate a first clock signal by performing clock recovery on the signals received from the first to third receivers;
a first latch section configured to generate a first data stream by latching the signals received from the first to third receivers in synchronization with the first clock signal; and
a first processing section configured to generate the first reception data based on the first data stream, and
wherein the D-PHY block comprises:
a second latch section configured to generate a second data stream by latching the signals received from the second and third receivers by using a first output signal output from the first receiver as a clock signal; and
a second processing section configured to generate the second reception data based on the second data stream.

3. The semiconductor device module according to claim 1 , further comprising:
seventh and eighth external connection terminals; and
a fourth receiver connected to the seventh and eighth external connection terminals,
wherein the C-PHY block comprises:
a clock recovery circuit configured to generate a first clock signal by performing clock recovery on the signals received from the first to third receivers;
a first latch section configured to generate a first data stream by latching the signals received from the first to third receivers in synchronization with the first clock signal; and
a first processing section configured to generate the first reception data based on the first data stream, and

wherein the D-PHY block comprises:
a second latch section configured to generate a second data stream by latching the signals received from the first to third receivers by using a first output signal output from the fourth receiver as a clock signal; and
a second processing section configured to generate the second reception data based on the second data stream.

4. The semiconductor device module according to claim 1 , further comprising:
a first capacitor connected between a first common connection node and a circuit ground;
a second capacitor connected between a second common connection node and the circuit ground;
a third capacitor connected between a third common connection node and the circuit ground;
a first resistor element connected between the first external connection terminal and a first node;
a first switch connected between the first node and the first common connection node;
a second resistor element;
a second switch, the second resistor element and the second switch being connected in series between the second external connection terminal and the first common connection node;
a third resistor element connected between the third external connection terminal and a second node;
a third switch connected between the second node and the second common connection node;
a fourth resistor element;
a fourth switch, the fourth resistor element and the fourth switch being connected in series between the fourth external connection terminal and the second common connection node;
a fifth resistor element connected between the fifth external connection terminal and a third node;
a fifth switch connected between the third node and the third common connection node;
a sixth resistor element;
a sixth switch, the sixth resistor element and the sixth switch being connected in series between the sixth external connection terminal and the third common connection node;
a fourth capacitor connected between a fourth common connection node and the circuit ground;
a seventh switch connected between the first node and the fourth common connection node;
an eighth switch connected between the second node and the fourth common connection node; and
a ninth switch connected between the third node and the fourth common connection node.

5. The semiconductor device module according to claim 1 , further comprising:
a first capacitor connected between a first common connection node and a circuit ground;
a second capacitor connected between a second common connection node and the circuit ground;
a third capacitor connected between a third common connection node and the circuit ground;
a first resistor element connected between the first external connection terminal and a first node;
a first switch connected between the first node and the first common connection node;
a second resistor element;
a second switch, the second resistor element and the second switch being connected in series between the first external connection terminal and the first common connection node;
a third resistor element connected between the second external connection terminal and a second node;
a third switch connected between the second node and the first common connection node;
a fourth resistor element;
a fourth switch, the fourth resistor element and the fourth switch being connected in series between the second external connection terminal and the first common connection node;
a fifth resistor element connected between the third external connection terminal and a third node;
a fifth switch connected between the third node and the second common connection node;
a sixth resistor element;
a sixth switch, the sixth resistor element and the sixth switch being connected in series between the third external connection terminal and the second common connection node;
a seventh resistor element connected between the fourth external connection terminal and a fourth node;
a seventh switch connected between the fourth node and the second common connection node;
an eighth resistor element;
an eighth switch, the eighth resistor element and the eighth switch being connected between the fourth external connection terminal and the second common connection node;
a ninth resistor element connected between the fifth external connection terminal and a fifth node;
a ninth switch connected between the fifth node and the third common connection node;
a tenth resistor element;
a tenth switch, the tenth resistor element and the tenth switch being connected in series between the fifth external connection terminal and the third common connection node;
an eleventh resistor element connected between the sixth external connection terminal and a sixth node;
an eleventh switch connected between the sixth node and the third common connection node;
a twelfth resistor element;
a twelfth switch, the twelfth resistor element and the twelfth switch being connected in series between the sixth external connection terminal and the third common connection node;
a fourth capacitor connected between a fourth common connection node and the circuit ground;
a thirteenth switch connected between the first node and the fourth common connection node;
a fourteenth switch connected between the second node an

Assignees

• Synaptics Japan Gk

Inventors

• Itoigawa Keiichi
• Hori Yoshihiko
• Kitamura Tomomitsu
• SENO Takefumi
• Kuwada Hideaki
• Tamura Takashi
• Kurosawa Jun
• Kanda Kazuhiko

Classifications

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G2352/00

  Parallel handling of streams of display data · CPC title

• H03L7/00

  Automatic control of frequency or phase; Synchronisation · CPC title

• G09G5/008

  Clock recovery · CPC title

• G09G2310/0202

  Addressing of scan or signal lines · CPC title