Memory and processor hierarchy to improve power efficiency

Patent metadata

Field	Value
Publication number	US-9959202-B2
Application number	US-201514855803-A
Country	US
Kind code	B2
Filing date	Sep 16, 2015
Priority date	Sep 16, 2014
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

A computing memory includes an execution unit and an access processor coupled with a memory system, where the execution unit and the access processor are logically separated units. The execution unit is for processing operand data. The access processor is for providing operand data and configuration data to the execution unit. The access processor reads operand data from the memory system and sends the operand data to the execution unit. The execution unit executes the operand data according to the provided configuration data. The access processor includes information about execution times of operations of the execution unit for the provided configuration. The access processor reserves time-slots for writing execution unit results provided by the execution unit into selected locations in the memory system based on the information about the execution times, upon sending at least one of the operand data and the configuration data to the execution unit.

First claim

What is claimed is:

1. A computing memory, comprising:
an execution unit for processing operand data; and
an access processor coupled with a memory system for providing operand and configuration data to the execution unit, wherein the execution unit and the access processor are logically separated units, and wherein the access processor reads operand data from the memory system and sends these data to the execution unit which executes operations on the operand data according to the provided configuration data, and wherein the access processor has information about execution times of operations of the execution unit for the provided configuration, and wherein the access processor reserves time-slots for writing execution unit results provided by the execution unit into selected locations in the memory system based on the information about the execution times, at the time of sending the data to the execution unit.

2. The computing memory according to claim 1 , wherein the execution unit is implemented as field programmable gate array.

3. The computing memory according to claim 1 , wherein the information about execution times of operations of the execution unit for a provided configuration is pre-calculated, pre-programmed or measured.

4. The computing memory according to claim 1 , wherein the access processor also provides a tag together with each operand and each configuration of the operand and configuration data.

5. The computing memory according to claim 4 , wherein the tag defines the type of data sent from the access processor to the execution unit.

6. The computing memory according to claim 5 , wherein the type of data defines at least one out of the group comprising operand data, execution configuration data or information about future use of operand data.

7. The computing memory according to claim 1 , wherein configuration data comprise a horizontal micro-code vector.

8. The computing memory according to claim 1 , wherein configuration data comprise a micro-program to be executed in the execution unit.

9. The computing memory according to claim 1 , wherein the access processor and the memory system are implemented in a three-dimensional chip with the access processor and the execution unit implemented in one layer and the memory system implemented in another layer.

10. The computing memory according to claim 1 , wherein the access processor and one or multiple execution units are implemented on the same layer as the memory system.

11. The computing memory according to claim 1 , wherein a second execution unit is more loosely coupled to the access processor than the first execution unit.

12. The computing memory according to claim 1 , wherein the computing memory comprises more than one execution unit.

13. The computing memory according to claim 12 , wherein only the execution unit in use is supplied with power.

14. A computing system, comprising:
a central processing unit; and
a computing memory acting as main memory for the central processing unit, the computer memory comprising:
an execution unit for processing operand data; and
an access processor coupled with a memory system for providing operand and configuration data to the execution unit, wherein the execution unit and the access processor are logically separated units, and wherein the access processor reads operand data from the memory system and sends these data to the execution unit which executes operations on the operand data according to the provided configuration data, and wherein the access processor has information about execution times of operations of the execution unit for the provided configuration, and wherein the access processor reserves time-slots for writing execution unit results provided by the execution unit into selected locations in the memory system based on the information about the execution times, at the time of sending the data to the execution unit.

15. The computing system according to claim 14 , wherein the execution unit is implemented as field programmable gate array.

16. The computing system according to claim 14 , wherein the information about execution times of operations of the execution unit for a provided configuration is pre-calculated, pre-programmed or measured.

17. The computing system according to claim 14 , wherein the access processor also provides a tag together with each operand and each configuration of the operand and configuration data.

18. The computing system according to claim 17 , wherein the tag defines the type of data sent from the access processor to the execution unit.

19. The computing system according to claim 18 , wherein the type of data defines at least one out of the group comprising operand data, execution configuration data or information about future use of operand data.

20. The computing system according to claim 14 , wherein configuration data comprise a horizontal micro-code vector.

Assignees

• IBM

Inventors

• Van Lunteren Jan
• Giefers Heiner

Classifications

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• G06F9/265

  by address selection on input of storage · CPC title

• G06F9/30007

  to perform operations on data operands · CPC title

• G06F9/3004

  to perform operations on memory · CPC title

• G06F12/02 Primary

  Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00) · CPC title